ADE7932 datasheet(43/120 Pages) AD

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Data Sheet

ADE7978/ADE7933/ADE7932

Rev. 0 | Page 43 of 120

If a ZXTOIx or ZXTOVx bit (any of Bits[8:3]) is set in the

MASK1 register, the IRQ1 interrupt pin is driven low when the

corresponding status bit is set to 1. The status bit is cleared and

the IRQ1 pin returns high when a 1 is written to the appropriate

bit in the STATUS1 register.

The resolution of the ZXTOUT register is 62.5 μs (16 kHz clock)

per LSB. Thus, the maximum timeout period for an interrupt is

4.096 sec, that is, 216/16 kHz. Note that because the timer starts

to decrement 1 ms after a zero-crossing event is triggered, the

value of the ZXTOUT register is

ZXTOUT = Desired ZX Timeout × 16 kHz − 16

(14)

Figure 54 shows the mechanism of zero-crossing timeout

detection when the voltage or current signal stays at a fixed

dc level for more than 62.5 μs × ZXTOUT μs.

16-BIT INTERNAL

ZXTOUT

VOLTAGE

CURRENT

SIGNAL

IRQ1 INTERRUPT PIN

ZXTOxy FLAG IN

STATUS1[31:0], x = V, I,

y = A, B, C

Figure 54. Zero-Crossing Timeout Detection

When the phase voltage is 0, noise in the voltage measurement

can trigger spurious zero-crossing events that may nullify the

action of the ZX timeout. A threshold 1000 times lower than full

scale is implemented in conjunction with this circuit. If the peak

of the phase voltage is below this threshold, the ZX timeout

counter begins to decrement automatically.

Phase Sequence Detection

The ADE7978 has on-chip phase sequence error detection circuits.

This detection works on phase voltages and considers only the

zero crossings determined by their negative to positive transitions.

The regular succession of these zero-crossing events is Phase A

followed by Phase B followed by Phase C (see Figure 55).

ZX C

ZX B

PHASE B

PHASE C

PHASE A

ZX A

Figure 55. Regular Succession of Zero-Crossing Events:

Phase A, Phase B, and Phase C

If the sequence of zero-crossing events is, instead, Phase A

followed by Phase C followed by Phase B, then Bit 19 (SEQERR)

in the STATUS1 register is set. If Bit 19 (SEQERR) in the MASK1

the IRQ1 interrupt pin is driven low. The status bit is cleared and

the IRQ1 pin returns high when a 1 is written to Bit 19 (SEQERR)

in the STATUS1 register.

The phase sequence error detection circuit is functional only

when the ADE7978/ADE7933/ADE7932 chipset is connected

in a 3-phase, 4-wire, three voltage sensor configuration (Bits[5:4],

CONSEL[1:0], in the ACCMODE register at Address 0xE701 are

set to 00). In all other configurations, only two voltage sensors

are used; therefore, it is not recommended to use the detection

circuit. In these configura-tions, use the time intervals between

phase voltages to analyze the phase sequence (see the Time

Interval Between Phases section).

Figure 56 shows an example of the Phase A voltage followed by

the Phase C voltage instead of the Phase B voltage. After this error

occurs, Bit 19 (SEQERR) in the STATUS1 register is set to 1

every time a negative to positive zero crossing occurs.

ZX B

ZX C

PHASE C

PHASE B

PHASE A

A, B, C PHASE

VOLTAGES AFTER

LPF1

BIT 19 (SEQERR) IN

STATUS1 REGISTER

IRQ1

ZX A

STATUS1[19] SET TO 1

STATUS1[19] CANCELLED

BY A WRITE TO

STATUS1 REGISTER WITH

SEQERR BIT SET

Figure 56. SEQERR Bit Set to 1 When Phase A Voltage Is Followed by

Phase C Voltage

After a phase sequence error is detected, the time measurement

between various phase voltages can help to identify which phase

voltage should be combined with another phase current in the

computational datapath (see the Time Interval Between Phases

section). Bits[9:8] (VTOIA[1:0]), Bits[11:10] (VTOIB[1:0]), and

Bits[13:12] (VTOIC[1:0]) in the CONFIG register (Address 0xE618)

can be used to direct one phase voltage to the datapath of another

phase (see the Changing the Phase Voltage Datapath section for

more information).

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