ADE7932 datasheet(45/120 Pages) AD

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Data Sheet

ADE7978/ADE7933/ADE7932

Rev. 0 | Page 45 of 120

PHASE VOLTAGE SAG DETECTION

The ADE7978 can be programmed to detect when the absolute

value of any phase voltage falls below or rises above a specified

peak value for a number of half line cycles. The phase in which

this event takes place and the state of the phase voltage relative

to the threshold is identified in Bits[14:12] (VSPHASE[x]) of the

PHSTATUS register (Address 0xE600). An associated interrupt is

triggered when any phase falls below or rises above a threshold.

Bit 6 (SAGCFG) in the ACCMODE register (Address 0xE701)

selects the way that Bit 16 (sag) in the STATUS1 register is

generated. If the SAGCFG bit is cleared to 0 (the default value),

the sag status bit is set to 1 when any phase voltage is below the

SAGLVL threshold. If the SAGCFG bit is set to 1, the sag status

bit is set to 1 only when a phase voltage goes below and then

above the SAGLVL threshold.

Figure 59 shows the behavior of the ADE7978 when the

SAGCFG bit is cleared to 0.

The Phase A voltage falls below the threshold set in

the sag level register (SAGLVL) for four half line cycles

(SAGCYC = 4).

When Bit 16 (sag) in the STATUS1 register is set to 1 to

indicate the condition, the VSPHASE[0] bit in the PHSTATUS

SAGLVL. The IRQ1 interrupt pin goes low.

The microcontroller writes a 1 to Bit 16 (sag) in the STATUS1

back high. The VSPHASE[0] bit in the PHSTATUS register

remains set.

The Phase A voltage continues to stay below the SAGLVL

threshold for four more half line cycles (SAGCYC = 4).

Bit 16 (sag) in the STATUS1 register is again set to 1. The

IRQ1 interrupt pin is again set low. The VSPHASE[0] bit

in the PHSTATUS register remains set.

During the next four half line cycles (SAGCYC = 4), the

Phase A voltage is above the SAGLVL threshold. The

VSPHASE[0] bit in the PHSTATUS register is cleared to 0

at the end of the SAGCYC period.

PHASE A VOLTAGE

FULL SCALE

SAGLVL[23:0]

SAGCYC[7:0] = 0x4

BIT 16 (SAG) IN

STATUS1[31:0]

VSPHASE[0] =

PHSTATUS[12]

IRQ1 PIN

STATUS1[16]

CANCELLED

BY A WRITE TO

STATUS1[31:0]

WITH SAG BIT SET

PHSTATUS[12]

REMAINS HIGH UNTIL

PHASE A VOLTAGE

GOES ABOVE SAGLVL

DURING ONE SAGCYC

IRQ1 PIN LOW

EVERY TIME

PHASE A VOLTAGE

STAYS BELOW

SAGLVL FOR

SAGCYC PERIOD

Figure 59. Sag Detection: SAGCFG Bit in ACCMODE Register Cleared to 0

Figure 60 shows the behavior of the ADE7978 when the

SAGCFG bit is set to 1.

The Phase A voltage falls below the threshold set in

the sag level register (SAGLVL) for four half line cycles

(SAGCYC = 4).

When Bit 16 (sag) in the STATUS1 register is set to 1 to

indicate the condition, the VSPHASE[0] bit in the PHSTATUS

SAGLVL. The IRQ1 interrupt pin goes low.

The microcontroller writes a 1 to Bit 16 (sag) in the

STATUS1 register to clear the bit and bring the IRQ1

interrupt pin back high. The VSPHASE[0] bit in the

PHSTATUS register remains set.

The Phase A voltage continues to stay below the SAGLVL

threshold for four more half line cycles (SAGCYC = 4).

Bit 16 (sag) in the STATUS1 register remains cleared to 0.

After four more half line cycles, the Phase A voltage rises

above the SAGLVL threshold.

Bit 16 (sag) in the STATUS1 register is set to 1. The IRQ1

interrupt pin is set low. The VSPHASE[0] bit in the

PHSTATUS register is cleared to 0.

PHASE A VOLTAGE

FULL SCALE

SAGLVL[23:0]

SAGCYC[7:0] = 0x4

BIT 16 (SAG) IN

STATUS1[31:0]

VSPHASE[0] =

PHSTATUS[12]

IRQ1 PIN

STATUS1[16]

CANCELLED

BY A WRITE TO

STATUS1[31:0]

WITH SAG BIT SET

PHSTATUS[12]

REMAINS HIGH UNTIL

PHASE A VOLTAGE

GOES ABOVE SAGLVL

DURING ONE SAGCYC

IRQ1 PIN LOW

WHEN PHASE A

VOLTAGE GOES

BELOW AND THEN

ABOVE SAGLVL

FOR SAGCYC

PERIOD

Figure 60. Sag Detection: SAGCFG Bit in ACCMODE Register Set to 1

The VSPHASE[1] and VSPHASE[2] bits configure the sag events

on Phase B and Phase C in the same way: when the Phase B or

Phase C voltage stays below SAGLVL during a SAGCYC period,

these bits are set to 1. When the phase voltages are above SAGLVL

during a SAGCYC period, the bits are set to 0.

The SAGCYC register (Address 0xE704) represents the number

of half line cycles during which the phase voltage must remain

below or above the level configured in the SAGLVL register

(Address 0xE509) to trigger a sag interrupt; 0 is not a valid value for

SAGCYC. For example, when the sag cycle bits (SAGCYC[7:0])

contain a value of 0x07, the sag flag in the STATUS1 register is

set at the end of the seventh half line cycle during which the line

voltage falls below the threshold.

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