ADE7932 datasheet(95/120 Pages) AD

95 / 120 page

Data Sheet

ADE7978/ADE7933/ADE7932

Rev. 0 | Page 95 of 120

SPI Read Operation

A read operation using the SPI interface of the ADE7978 is

initiated when the master sets the SS pin low and begins sending

one byte, representing the address of the ADE7978, on the MOSI

line (see Figure 121). The master sends data on the MOSI line

starting with the first high to low transition of SCLK. The SPI

interface of the ADE7978 samples the data on the low to high

transitions of SCLK.

The most significant seven bits of the address byte can have any

value, but as a good programming practice, these bits should have

a value other than 0111000, which is the 7-bit address used in the

I2C protocol. Bit 0 of the address byte is the read/write bit. For a

read operation, Bit 0 must be set to 1. The master then sends the

16-bit address of the register that is to be read. After the ADE7978

receives the last bit of the register address on a low to high tran-

sition of SCLK, it begins to transmit the register contents on the

MISO line when the next SCLK high to low transition occurs;

the master samples the data on a low to high SCLK transition.

After the master receives the last bit, it sets the SS and SCLK

lines high, and the communication ends. The data lines, MOSI

and MISO, enter a high impedance state.

SPI Burst Read Operation

The registers from Address 0xE50C to Address 0xE526 represent

quantities computed by the ADE7978 every 8 kHz (see the I2C

Burst Read Operation section for the list of registers).

These registers can be read in two ways: one register at a time (see

the SPI Read Operation section) or multiple consecutive registers

at a time in a burst mode.

Burst mode is initiated when the master sets the SS pin low and

begins sending one byte, representing the address of the ADE7978,

on the MOSI line (see Figure 122). The address is the same address

byte used for reading a single register. The master sends data on

the MOSI line starting with the first high to low transition of

SCLK. The SPI interface of the ADE7978 samples data on the

low to high transitions of SCLK.

The master sends the 16-bit address of the first register in the burst

to be read. Any register from Address 0xE50C to Address 0xE526

can be the first register in the burst. After the ADE7978 receives

the last bit of the register address on a low to high transition of

SCLK, it begins to transmit the register contents on the MISO line

when the next SCLK high to low transition occurs; the master

samples the data on a low to high SCLK transition.

After the master receives the last bit of the first register, the

ADE7978 sends the contents of the register placed at the next

location. This process is repeated until the master sets the SS

and SCLK lines high and the communication ends. The data

lines, MOSI and MISO, enter a high impedance state.

Address 0xE526 is the last location of the memory range allocated

to the burst read operation. Do not perform a burst read operation

on register locations with addresses greater than 0xE526.

The high to low transition of the ZX/DREADY pin can be used

to initiate a burst read operation. The pin must be configured for

the DREADY functionality (set Bits[1:0], ZX_DREADY, to 00

in the CONFIG register, Address 0xE618). The ZX/DREADY

pin goes low approximately 70 ns after Bit 17 (DREADY) in the

STATUS0 register (Address 0xE502) is set to 1. The pin stays

low for 10 µs and then goes high again.

15 14

SCLK

MOSI

MISO

31 30

Figure 121. SPI Read Operation of a 32-Bit Register

SCLK

MOSI

MISO

ADDRESS

VALUE

Figure 122. SPI Burst Read of Consecutive Registers Located Between Address 0xE50C and Address 0xE526

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