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ADE7932 数据表(PDF) 59 Page - Analog Devices

部件名 ADE7932
功能描述  Isolated Energy Metering Chipset for Polyphase Shunt Meters
PDF  120 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
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ADE7932 数据表(HTML) 59 Page - Analog Devices

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Data Sheet
ADE7978/ADE7933/ADE7932
Rev. 0 | Page 59 of 120
SIGN OF REACTIVE POWER CALCULATION
The reactive power is a signed calculation. Table 24 summarizes
the relationship between the phase difference between the voltage
and the current and the sign of the resulting reactive power
calculation.
Table 24. Sign of Reactive Power Calculation
Φ1
Sign of Reactive Power
From 0 to +180
Positive
From −180 to 0
Negative
1
Φ is defined as the phase angle of the voltage signal minus the current
signal; that is, Φ is positive if the load is inductive and negative if the load
is capacitive.
The ADE7978 has sign detection circuitry for reactive power
calculations; this circuitry can monitor the total reactive powers
or the fundamental reactive powers. As described in the Reactive
Energy Calculation section, the reactive energy accumulation is
performed in two stages. Each time a sign change is detected in
the energy accumulation at the end of the first stage—that is, after
the energy accumulated in the internal accumulator reaches the
VARTHR register threshold—a dedicated interrupt is triggered.
The sign of each phase reactive power can be read in the PHSIGN
register (Address 0xE617).
Bit 1 (REVRPSEL) in the MMODE register (Address 0xE700)
specifies the type of reactive power that is monitored. When
REVRPSEL is cleared to 0 (the default value), the total reactive
power is monitored. When REVRPSEL is set to 1, the funda-
mental reactive power is monitored.
Bits[12:10] (REVRPC, REVRPB, and REVRPA) in the STATUS0
register are set when a sign change occurs in the power selected
by Bit 1 (REVRPSEL) in the MMODE register.
Bits[6:4] (CVARSIGN, BVARSIGN, and AVARSIGN) in the
PHSIGN register are set simultaneously with the REVRPC,
REVRPB, and REVRPA bits in the STATUS0 register. The
xVARSIGN bits indicate the sign of the reactive power. When
these bits are set to 0, the reactive power is positive. When the
bits are set to 1, the reactive power is negative.
The REVRPx bits in the STATUS0 register and the xVARSIGN
bits in the PHSIGN register refer to the reactive power of
Phase x and the power type selected by Bit 1 (REVRPSEL) in
the MMODE register.
Interrupts attached to Bits[12:10] (REVRPC, REVRPB, and
REVRPA) in the STATUS0 register can be enabled by setting
Bits[12:10] in the MASK0 register. When enabled, the IRQ0 pin
goes low and the status bit is set to 1 when a change of sign occurs.
To identify the phase that triggered the interrupt, read the PHSIGN
register immediately after reading the STATUS0 register. The status
bit is cleared and the IRQ0 pin is returned high by writing a 1 to
the appropriate bits in the STATUS0 register.
REACTIVE ENERGY CALCULATION
Reactive energy is defined as the integral of reactive power.
Reactive Energy =
dt
q(t)
(37)
Similar to active power, the ADE7978 achieves the integration
of the reactive power signal in two stages (see Figure 79). The
process is identical for total reactive power and fundamental
reactive power.
The first stage accumulates the instantaneous phase total or
fundamental reactive power at 1.024 MHz (the DSP computes
these values at an 8 kHz rate). Each time a threshold is reached,
a pulse is generated, and the threshold is subtracted from the
internal register. The sign of the energy at this moment is con-
sidered the sign of the reactive power (see the Sign of Reactive
Power Calculation section for more information).
The second stage consists of accumulating the pulses generated
at the first stage into internal 32-bit accumulation registers. The
contents of these registers are transferred to the var-hour registers
(xVARHR and xFVARHR) when these registers are accessed.
AVARHR, BVARHR, CVARHR, AFVARHR, BFVARHR, and
CFVARHR represent phase total and fundamental reactive
powers. Figure 79 shows this process.
INTERNAL
ACCUMULATOR
VARACC BITS IN
ACCMODE[7:0]
THRESHOLD
DIGITAL SIGNAL PROCESSOR
TOTAL
REACTIVE
POWER
ALGORITHM
APGAIN
AVAROS
24
AVAR
:
VARTHR
34
27 26
0
0
32-BIT REGISTER
AVARHR[31:0]
REVRPA BIT IN
STATUS0[31:0]
CURRENT SIGNAL
FROM HPF
VOLTAGE SIGNAL
FROM HPF
Figure 79. Total Reactive Energy Accumulation



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