ADE7932 datasheet(48/120 Pages) AD

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ADE7978/ADE7933/ADE7932

Data Sheet

Rev. 0 | Page 48 of 120

Overvoltage and Overcurrent Level Setting

The contents of the 24-bit unsigned overvoltage (OVLVL) and

overcurrent (OILVL) registers are compared to the absolute value

of the voltage and current channels. The maximum value of these

registers is the maximum value of the HPF outputs: 5,320,000.

When the OVLVL or OILVL register is equal to this value, the

overvoltage or overcurrent conditions are never detected. Writing

0x0 to these registers signifies that the overvoltage or overcurrent

condition is continuously detected, and the corresponding

interrupt is permanently triggered.

The serial ports of the ADE7978 work with 32-, 16-, or 8-bit

words. Like the SAGLVL register, the OILVL and OVLVL registers

are transmitted as 32-bit registers with the eight MSBs padded

with 0s (see Figure 61).

NEUTRAL CURRENT MISMATCH

In 3-phase systems, the neutral current is equal to the algebraic

sum of the phase currents.

IN(t) = IA(t) + IB(t) + IC(t)

If there is a mismatch between these two quantities, a tamper

situation may have occurred in the system.

The ADE7978 computes the sum of the phase currents by

adding the contents of the IAWV, IBWV, and ICWV registers

(Address 0xE50C to Address 0xE50E) and storing the result in

the 28-bit signed ISUM register (Address 0x43CA).

ISUM(t) = IA(t) + IB(t) + IC(t)

The ISUM value is computed every 125 µs (8 kHz frequency), the

rate at which the current samples are available. Bit 17 (DREADY)

in the STATUS0 register is used to signal when the ISUM register

can be read. For more information about the DREADY bit, see

the Digital Signal Processor section.

To recover the ISUM(t) value from the ISUM register, use the

following equation:

MAX

SUM

ADC

ISUM[27:0]

)

(

where:

ADCMAX = 5,320,000, the ADC output when the input is

at full scale.

IFS is the full-scale ADC phase current.

Note that the ADE7978 also computes the rms of ISUM and

stores it in the NIRMS register (Address 0x43C9) when Bit 14

(INSEL) in the CONFIG register is set to 1. For more informa-

tion, see the Current RMS Calculation section.

When Bits[5:4] (CONSEL[1:0]) in the ACCMODE register are

set to 01 (meter functions in a 3-wire delta configuration), the

Phase B ADE7933/ADE7932 is not connected, and the IBWV

value output by the HPF is 0. In this case, ISUM represents a

negative estimate of the Phase B current (−IBWV). The NIRMS

(INSEL) in the CONFIG register is set to 1.

The ADE7978 computes the difference between the absolute values

of ISUM and the neutral current from the INWV register, takes the

absolute value, and compares it against the threshold configured

in the ISUMLVL register (Address 0x4398).

If ||ISUM| − |INWV|| ≤ |ISUMLVL|, it is assumed that the

neutral current is equal to the sum of the phase currents and

that the system is functioning properly.

If ||ISUM| − |INWV|| > |ISUMLVL|, a tamper situation may have

occurred, and Bit 20 (MISMTCH) in the STATUS1 register is set

to 1. An interrupt attached to the flag can be enabled by setting

Bit 20 (MISMTCH) in the MASK1 register. If the interrupt is

enabled, the IRQ1 pin is set low when the MISMTCH status bit

is set to 1. The status bit is cleared and the IRQ1 pin returns high

by writing a 1 to Bit 20 (MISMTCH) in the STATUS1 register.

If ||ISUM| − |INWV|| ≤ |ISUMLVL|, the MISMTCH bit = 0.

If ||ISUM| − |INWV|| > |ISUMLVL|, the MISMTCH bit = 1.

ISUMLVL, the positive threshold used in the process, is a 24-bit

signed register. Because it is used in a comparison with an absolute

value, always set ISUMLVL to a positive value from 0x00000 to

0x7FFFFF. ISUMLVL uses the same scale as the outputs of the

current ADCs; therefore, writing 5,320,000 to the ISUMLVL

Current Channel ADC section for more information). Writing

0x000000 (the default value) or a negative value to the ISUMLVL

Write the correct value for the application to the ISUMLVL

avoid continuously triggering MISMTCH events.

The serial ports of the ADE7978 work with 32-, 16-, or 8-bit

words, whereas the DSP works with 28-bit words. The 28-bit

signed ISUM register is transmitted as a 32-bit register with the

four MSBs padded with 0s (see Figure 65).

28 27

BIT 27 IS A SIGN BIT

28-BIT SIGNED NUMBER

0000

Figure 65. 28-Bit ISUM Register Transmitted as a 32-Bit Word

Like the xIGAIN registers shown in Figure 44, the ISUMLVL

transmission as a 32-bit register.

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