AD9549APCBZ datasheet(33/76 Pages) AD

33 / 76 page

AD9549

Rev. D | Page 33 of 76

FDBK_IN INPUTS

The feedback pins, FDBK_IN and FDBK_INB, serve as the input

to the feedback path of the digital PLL. Typically, these pins are

used to receive the signal generated by the DDS after it has been

band-limited by the external reconstruction filter.

A diagram of the FDBK input pins is provided in Figure 40,

which includes some of the internal components used to bias

the input circuitry. Note that the FDBK input pins are internally

biased to a dc level of ~1 V. Care should be taken to ensure that

any external connections do not disturb the dc bias because this

may significantly degrade performance.

15k

Ω

15k

Ω

~1pF

TO S-DIVIDER

AND CLOCK

OUTPUT SECTION

VSS

~1V

VSS

~2pF

FDBK_IN

FDBK_INB

Figure 40. Differential FDBK Inputs

REFERENCE INPUTS

Reference Clock Receiver

The reference clock receiver is the point at which the user

supplies the input clock signal that the synchronizer synthesizes

into an output clock. The clock receiver circuit is able to handle

a relatively broad range of input levels as well as frequencies

from 8 kHz up to 750 MHz.

Figure 41 is a diagram of the REFA and REFB input pins, which

includes some of the internal components used to bias the input

circuitry. Note that the REF input pins are internally biased by a

dc source, VB. Care should be taken to ensure that any external

connections do not disturb the dc bias because such a disturbance

may significantly degrade performance.

Note that support for redundant reference clocks is achieved by

using the two reference clock receivers (REFA and REFB).

Ω

~1pF

TO REFERENCE

MONITOR AND

SWITCHING LOGIC

VSS

REFA_IN

(OR REFB_IN)

REFA_INB

(OR REFB_INB)

VDD

1pF

GND

Figure 41. Reference Inputs

To accommodate a variety of input signal conditions, the value

of VB is programmable via a pair of bits in the I/O register map.

Table 6 gives the value of VB for the bit pattern in Register 0x040F.

Table 6. Setting of Input Bias Voltage (VB)

Reference Bias Level, Register 0x040F[1:0]

00 (default)

AVDD3 − 800 mV

AVDD3 − 400 mV

AVDD3 − 1600 mV

AVDD3 − 1200 mV

SYSCLK INPUTS

Functional Description

The SYSCLK pins are where an external time base is connected

to the AD9549 for generating the internal high frequency

system clock (fS).

The SYSCLK inputs can be operated in one of three modes:

•

SYSCLK PLL bypassed

•

SYSCLK PLL enabled with input signal generated externally

•

Crystal resonator with SYSCLK PLL enabled

A functional diagram of the system clock generator is shown in

Figure 42.

BIPOLAR

EDGE

DETECTOR

WITH CRYSTAL

RESONATOR

SYSCLK

PLL

ENABLED

WITH EXTERNAL DRIVE

SYSCLK PLL BYPASSED

SYSCLK

PLL

MULTIPLIER

2× REFERENCE FREQUENCY DOUBLER

(I/O REGISTER BIT)

PD SYSCLK PLL

(I/O REGISTER BIT)

DAC

SAMPLE

CLOCK

LOOP_FILTER

SYSCLK

SYSCLKB

CLKMODESEL

Figure 42. System Clock Generator Block Diagram

AD9549APCBZ 数据表(PDF) 33 Page - Analog Devices

AD9549APCBZ 数据表(HTML) 33 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

数据表下载

链接网址

AD9549APCBZ 数据表(PDF) 33 Page - Analog Devices

AD9549APCBZ 数据表(HTML) 33 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

数据表 下载

链接网址

数据表下载