AD9549APCBZ datasheet(7/76 Pages) AD

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AD9549

Rev. D | Page 7 of 76

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CMOS Output Driver

(AVDD3/Pin 37) @ 3.3 V

Frequency Range

0.008

150

MHz

See

Figure 14 for maximum toggle rate

Duty Cycle

With 20 pF load and up to 150 MHz

Rise Time/Fall Time (20-80%)

4.6

With 20 pF load

CMOS Output Driver

(AVDD3/Pin 37) @ 1.8 V

Frequency Range

0.008

MHz

See

Figure 13 for maximum toggle rate

Duty Cycle

With 20 pF load and up to 40 MHz

Rise Time/Fall Time (20% to 80%)

6.8

With 20 pF load

HOLDOVER

Frequency Accuracy

See the

Holdover section

OUTPUT FREQUENCY SLEW LIMITER

Slew Rate Resolution

0.54

111

Hz/sec

P = 216 for minimum; P = 25 for maximum

Slew Rate Range

3 × 1016

Hz/sec

P = 216 for minimum; P = 25 for maximum

REFERENCE MONITORS

Loss of Reference Monitor

Operating Frequency Range

7.63 × 103

167 × 106

Minimum Frequency Error for

Continuous REF Present Indication

−16

ppm

fREF = 8 kHz

Minimum Frequency Error for

Continuous REF Present Indication

−19

fREF = 155 MHz

Maximum Frequency Error for

Continuous REF Lost Indication

−32

ppm

fREF = 8 kHz

Maximum Frequency Error for

Continuous REF Lost Indication

−35

fREF = 155 MHz

Reference Quality Monitor

Operating Frequency Range

0.008

150

MHz

Frequency Resolution (Normalized)

0.2

ppm

fREF = 8 kHz; OOL divider = 65,535 for minimum; OOL

divider = 1 for max (see the

Reference Frequency

Monitor section)

Frequency Resolution (Normalized)

408

ppm

fREF = 155 MHz; OOL divider = 65,535 for minimum;

OOL divider = 1 for maximum

Validation Timer

See the

Reference Validation Timers section

Timing Range

32 × 10−9

137

sec

PIO = 5

Timing Range

65 × 10−6

2.8 × 105

sec

PIO = 16

DAC OUTPUT CHARACTERISTICS

DCO Frequency Range (1st Nyquist Zone)

450

MHz

DPLL loop bandwidth sets lower limit

Output Resistance

Ω

Single-ended (each pin internally terminated to AVSS)

Output Capacitance

Full-Scale Output Current

31.7

Range depends on DAC RSET resistor

Gain Error

−10

+10

% FS

Output Offset

0.6

μA

Voltage Compliance Range

AVSS −

0.50

+0.5

AVSS +

0.50

Outputs not dc-shorted to VSS

DIGITAL PLL

Minimum Open-Loop Bandwidth

0.1

Dependent on the frequency of REFA/REFB, the DAC

sample rate, and the P-, R-, and S-divider values

Maximum Open-Loop Bandwidth

100

kHz

Dependent on the frequency of REFA/REFB, the DAC

sample rate, and the P-, R-, and S-divider values

Minimum Phase Margin

Degrees

Dependent on the frequency of REFA/REFB, the DAC

sample rate, and the P-, R-, and S-divider values

Maximum Phase Margin

Degrees

Dependent on the frequency of REFA/REFB, the DAC

sample rate, and the P-, R-, and S-divider values

PFD Input Frequency Range

~0.008

~24.5

MHz

Feedforward Divider Ratio

131,070

1, 2, …, 65,535 or 2, 4, …, 131,070

Feedback Divider Ratio

131,070

1, 2, …, 65,535 or 2, 4, …, 131,070

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