AD9549APCBZ datasheet(42/76 Pages) AD

42 / 76 page

AD9549

Rev. D | Page 42 of 76

POWER-UP

POWER-ON RESET

On initial power-up, it is recommended that the user apply a

RESET pulse, at least 75 ns in duration, on Pin 59 after both of

the following two conditions are met:

•

The 3.3 V supply is greater than 2.35 V ± 0.1 V.

•

The 1.8 V supply is greater than 1.4 V ± 0.05 V.

The high-to-low transition of the RESET pulse is the active

edge of the pulse and therefore the user is afforded the option

of holding RESET high during power–up.

Less than 1 ns after RESET goes high, the S1 to S4 configuration

pins go high impedance and remain high impedance until RESET

is deactivated. This allows strapping and configuration during

RESET.

Because of this reset sequence, external power supply sequenc-

ing is not critical.

PROGRAMMING SEQUENCE

The following sequence should be used when initializing the

AD9549:

1. Apply power. After the power supplies reach a threshold and

stabilize, it is recommended that an active high pulse be

asserted on the RESET pin (Pin 59), initiating a hard reset.

2. It is important to be sure that the desired configuration

registers have single-tone mode set (Register 0x0100, Bit 5)

and that the close loop bit (Register 0x0100[0]) is cleared.

If the close loop bit is set on initial loading, the AD9549

attempts to lock the loop before it has been configured.

3. When the registered are loaded, the OOL (out of limits)

and LOR (loss of reference) can be monitored to ensure

that a valid reference signal is present on REFA or REFB.

If a valid reference is present, Register 0x0100 can be

reprogrammed to clear single-tone mode and lock the loop.

4. Automatic holdover mode can then be used to make the

AD9549 immune to any disturbance on the reference inputs.

Use the following sequence when changing frequencies in the

AD9549:

1. Open the loop and enter single-tone mode via

2. Enter the new register settings.

3. Write 0x1E to Register 0x0012.

4. When the registers are loaded, the OOL (out of limits) and

LOR (loss of reference) can be monitored to ensure that

a valid reference signal is present on REFA or REFB.

5. If a valid reference is present, Register 0x0100 can be repro-

grammed to clear single-tone mode and lock the loop.

6. Automatic holdover mode can then be used to make the

AD9549 immune to any disturbance on the reference

inputs.

Note the following:

•

Attempting to lock the loop without a valid reference can

put the AD9549 into a state that requires a reset, or at a

minimum, writing 0xFF to Register 0x0012.

•

Automatic holdover mode is not available unless the loop

has been successfully closed.

•

If the user desires to open and close the loop manually, it is

recommended that 0x1E to be written to Register 0x0012

prior to closing the loop again.

AD9549APCBZ 数据表(PDF) 42 Page - Analog Devices

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