AD9549APCBZ datasheet(29/76 Pages) AD

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AD9549

Rev. D | Page 29 of 76

When calculating frequency error for a hitless switchover

environment such as Stratum 3, as defined in Telcordia

GR-1244-CORE, the designer must consider the frequency

error budget for the entire system. The frequency disturbance

caused by a reference clock switchover in the AD9549

contributes to this budget.

It is also critical that the designer differentiate between appli-

cations that require the output clock to track the input clock,

as opposed to applications that require the PLL to smooth out

transient disturbances on the input.

Based on all of the preceding considerations, the AD9549

digital PLL architecture allows the designer to choose a loop

bandwidth tailored to meet the requirements for a given

application. The loop bandwidth can range from 0.1 Hz up

to 100 kHz, provided that the loop bandwidth is never more

than 1/10th of the phase detector frequency.

HOLDOVER

Holdover Control and Frequency Accuracy

Holdover functionality provides the user with a means of

maintaining the output clock signal even in the absence of a

reference signal at the REFA or REFB input. In holdover mode,

the output clock is generated from the SYSCLK input (via the

DDS) by directly applying a frequency tuning word to the DDS.

The frequency accuracy of the AD9549 is exactly the frequency

accuracy of the system clock input.

Transfer from normal operation to holdover mode can be

accomplished either manually or automatically by appropriately

programming the automatic holdover bit (Register 0x01C0, Bit 0,

0 = manual, 1 = auto). The actual transfer to holdover operation,

however, depends on the state of the HOLDOVER pin and the

state of the enable holdover override and holdover on/off

control register bits (Register 0x01C1, Bits 1:0).

Manual holdover is established when the automatic holdover bit is

a Logic 0 (default). In manual mode, holdover is determined by

the state of the HOLDOVER pin (0 = normal, 1 = holdover). The

HOLDOVER pin is configured as a high impedance (>100 kΩ)

input pin to accommodate manual holdover operation.

Automatic holdover is invoked when the automatic holdover bit

is a Logic 1. In automatic mode, the HOLDOVER pin is configured

as a low impedance output with its logic state indicating the

holdover state as determined by the internal state machine

(0 = normal, 1 = holdover).

In automatic holdover operation, the user can override the internal

state machine by programming the enable holdover override bit

to a Logic 1 and the holdover mode bit (Register 0x001C0[4])

to the desired state (0 = normal, 1 = holdover). However, the

HOLDOVER pin does not indicate the forced holdover state in

the override condition but continues to indicate the holdover

state as chosen by the internal state machine (even though the

state machine choice is overridden). This allows the user to

force a holdover state by means of the programming registers

while monitoring the response of the state machine via the

HOLDOVER pin. A diagram of the reference switchover and

holdover logic is shown in Figure 33.

Note that the default state for the reference switchover bits is as

follows: automatic holdover = 0, enable holdover override = 0,

and holdover mode = 0.

AD9549APCBZ 数据表(PDF) 29 Page - Analog Devices

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