AD9549APCBZ datasheet(64/76 Pages) AD

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AD9549

Rev. D | Page 64 of 76

MONITOR (REGISTER 0x0300 TO REGISTER 0x0335)

This register contains the status of the chip. This register is read-only and live update.

Table 74.

Bits

Bit Name

Description

Reserved

Reserved.

PFD frequency too high

This flag indicates that the frequency estimator failed and detected a PFD frequency that is too high.

This bit is relevant only if the user is relying on the frequency estimator to determine the input

frequency.

PFD frequency too low

This flag indicates that the frequency estimator failed and detected a PFD frequency that is too low.

This bit is relevant only if the user is relying on the frequency estimator to determine the input

frequency.

Frequency estimator done

True when the frequency estimator circuit has successfully estimated the input frequency. See the

Frequency Estimator section.

Reference selected

Reference selected.

0 = Reference A is active.

1 = Reference B is active.

Free run

DPLL is in holdover mode (free run).

Phase lock detect

This flag indicates that the phase lock detect circuit has detected phase lock. The amount of phase

adjustment is compared against a programmable threshold. Note that this bit can be set in single

tone and holdover modes and should be ignored in these cases.

Frequency lock detect

This flag indicates that the frequency lock detect circuit has detected frequency lock. This feature

compares the absolute value of the difference of two consecutive phase detector edges against a

programmable threshold. Because of this, frequency lock detect is more rigorous than phase lock

detect, and it is possible to have phase lock detect without frequency lock detect.

This register contains the status of the chip. This register is read-only and live update.

Table 75.

Bits

Bit Name

Description

Reserved

Reserved.

REFA valid

The reference validation circuit has successfully determined that Reference A is valid.

REFA LOR

A LOR (loss of reference) has occurred on Reference A.

REFA OOL

The OOL (out of limits) circuit has determined that Reference A is out of limits.

Reserved

Reserved.

REFB Valid

The reference validation circuit has successfully determined that Reference B is valid.

REFB LOR

A LOR (loss of reference) has occurred on Reference B.

REFB OOL

The OOL (out of limits) circuit has determined that Reference B is out of limits.

These registers contain the chip status (Registers 0x0300 and Register 0x0301) at the time of IRQ. These bits are cleared with an IRQ reset

(see Register 0x0012, Bit 5).

Table 76.

Bits

Bit Name

Description

[7:3]

Reserved

Reserved.

Reference changed

Trigger IRQ when active reference clock selection changes.

Leave free run

Trigger IRQ when DPLL leaves free-run (holdover) mode.

Enter free run

Trigger IRQ when DPLL enters free-run (holdover) mode.

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