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AD9549APCBZ 数据表(PDF) 52 Page - Analog Devices

部件名 AD9549APCBZ
功能描述  Dual Input Network Clock Generator/Synchronizer
PDF  76 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9549APCBZ 数据表(HTML) 52 Page - Analog Devices

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AD9549
Rev. D | Page 52 of 76
Addr
(Hex)
Type1
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
BIt 2
Bit 1
Bit 0
Default
(Hex)
Calibration (user-accessible trim)
0x0400
K-divider
K-divider, Bits[15:0]
0x01
0x0401
0x00
0x0402
M
CPFD gain
CPFD gain scale, Bits[2:0]
0x00
0x0403
M
CPFD gain, Bits[5:0]
0x20
0x0404
FPFD gain
FPFD gain, Bits[7:0]
0xC8
0x0405
Reserved
Reserved
0x0406
RO
Part
version
Part
version
Part
version
Reserved
0x00 or
0x40
0x0407
Reserved
Reserved
0x0408
0x0409
M
PFD offset
DPLL phase offset, Bits[7:0]
0x00
0x040A
M
DPLL phase offset, Bits[13:8]
0x00
0x040B
DAC
full-scale
current
DAC full-scale current, Bits[7:0]
0xFF
0x040C
DAC full-scale current,
Bits[9:8]
0x01
0x040D
Reserved
Reserved
0x040E
Reserved
Reserved
0x10
0x040F
Reference
bias level
DC input level, Bits[1:0]
0x00
0x0410
Reserved
Reserved
Harmonic spur reduction
0x0500
M
Spur A
HSR-A
enable
Amplitude
gain × 2
Reserved
Spur A harmonic, Bits[3:0]
0x00
0x0501
M
Spur A magnitude, Bits[7:0]
0x00
0x0502
M
0x00
0x0503
M
Spur A phase, Bits[7:0]
0x00
0x0504
M
Spur A
phase,
Bit 8
0x00
0x0505
M
Spur B
HSR-B
enable
Amplitude
gain × 2
Reserved
Spur B harmonic[3:0]
0x00
0x0506
M
Spur B magnitude, Bits[7:0]
0x00
0x0507
M
0x00
0x0508
M
Spur B phase, Bits[7:0]
0x00
0x0509
M
Spur B
phase,
Bit 8
0x00
1 Types of registers: RO = read-only, AC = autoclear, M = mirrored (also called buffered). A mirrored register needs an I/O update for the new value to take effect.



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