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AD9549APCBZ 数据表(PDF) 22 Page - Analog Devices |
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AD9549APCBZ 数据表(HTML) 22 Page - Analog Devices |
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22 / 76 page  AD9549 Rev. D | Page 22 of 76 Phase Detector Gain Matching Although the fine and coarse phase detectors use different means to make a timing measurement, it is essential that both have equivalent phase gain. Without proper gain matching, the closed-loop dynamics of the system cannot be properly controlled. Hence, the goal is to make PhaseGainCPD = PhaseGainFPD. This leads to Gain FPFD PDG f PDS S _ ) 10 2 ( ) 2 ( 7 10 6 × = + which simplifies to S PDS f Gain FPFD PDG _ ) 10 16 ( 2 7 × = Typically, FPFD_Gain is established first, and then PDG and PDS are calculated. The proper choice for PDS is given by × = S f Gain FPFD PDS 2 _ 10 log round 7 2 The final value of PDS must satisfy 0 ≤ PDS ≤ 7. The proper choice for PDG is calculated using the following equation: = − S PDS f Gain FPFD PDG 4 7 2 _ 10 round The final value of PDG must satisfy 0 ≤ PDG ≤ 63. For example, let fS = 700 MHz and FPFD_Gain = 200; then PDS = 1 and PDG = 23. Note that the AD9549 evaluation software calculates register values that have the phase detector gains already matched. Phase Detector Pin Connections There are three pins associated with the phase detector that must be connected to external components. Figure 27 shows the recommended component values and their connections. 10µF 0.1µF PFD_VRT PFD_RSET PFD_VRB AD9549 0.1µF 0.1µF 4.99k Ω 20 21 22 Figure 27. Phase Detector Pin Connections DIGITAL LOOP FILTER COEFFICIENTS To provide the desired flexibility, the loop filter has been designed with three programmable coefficients (α, β, and γ). The coefficients, along with P (where P = 2PIO), completely define the response of the filter, which is given by + + − − + − − + = ) 1 ( ) 2 ( ) 1 ( ) ( 2 γ e γ e γ β e α ω H jω ω j jω LoopFilter To evaluate the response in terms of absolute frequency, substitute S f Pf ω π = 2 where P is the divide ratio of the P-divider, fS is the DAC sample rate, and f is the frequency at which the function is to be evaluated. The loop filter coefficients are determined by the AD9549 evaluation software according to three parameters: • Φ is the desired closed-loop phase margin (0 < Φ< π/2 rad). • fLOOP is the desired open-loop bandwidth (Hz). • fDDS is the desired output frequency of the DDS (Hz). Note that fDDS can also be expressed as fDDS = fR(S/R). The three coefficients are calculated according to parameters via the following equations: ) tan( 4 Φ Pf β C π − = β Φ F γ ) ( 2 1 = β Φ F f f Gain FPFD α C DDS ) ( _ 10 2 7 38 π − = where: ) sin( 1 1 ) ( Φ Φ F + = S LOOP C f f f = FPFD_Gain is the value of the gain scale factor for the fine phase detector as programmed into the I/O register map. Note that the range of loop filter coefficients is limited as follows: 0 < α < 223 (~8.39 × 106) −0.125 < β < 0 −0.125 < γ < 0 The preceding constraints on β and γ constrain the closed-loop phase margin such that both β and γ assume negative values. Even though β and γ are limited to negative quantities, the values as programmed are positive. The negative sign is assumed internally. Note that the closed-loop phase margin is limited to the range of 0° < Φ < 90° because β and γ are negative. |
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