AD9549APCBZ datasheet(25/76 Pages) AD

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AD9549

Rev. D | Page 25 of 76

The phase lock detect signal is generated once the control logic

observes that the output of the comparator has been in the true

state for 2x periods of the P-divider clock (see the Digital Loop

Filter section for a description of the P-divider). When the phase

lock detect signal is asserted, it remains asserted until cleared

by an unlock event or by a device reset.

The duration of the lock detection process is programmable via

the phase lock watchdog timer bits. The interval is controlled by a

5-bit number, X (0 ≤ X ≤ 20).The absolute duration of the

phase lock detect interval is

LOCK

Hysteresis in the phase lock detection process is controlled by

specifying the minimum duration that qualifies as an unlock

event. An unlock event is declared when the control logic

observes that the output of the comparator has been in the false

state for 2Y + 1 periods of the P-divider clock (provided that the

phase lock detect signal has been asserted). Detection of an

unlock event clears the phase lock detect signal, and the phase

lock detection process is automatically restarted.

The time required to declare an unlock event is programmable

via the phase unlock watchdog timer bits. The interval is

controlled by a 3-bit number, Y (0 ≤ Y ≤ 7). The absolute

duration of the unlock detection interval is

UNLOCK

Figure 31 shows the basic timing relationship between the

reference signal at the input to the phase detector, the phase

error magnitude, the output of the comparator, and the output

of the phase lock detector. The example shown here assumes

that X = 3 and Y = 1.

Note that the phase and frequency lock detectors may erroneously

indicate phase/frequency lock while in holdover. Therefore, the

user should use the phase and frequency lock signals in conjunc-

tion with either the reference input valid or the holdover active

signals to indicate phase/frequency lock.

Frequency Lock Detection

Frequency lock detection is similar to phase lock detection, with

the exception that the difference between successive phase

samples is the source of information. A running difference of

the phase samples serves as a digital approximation to the time-

derivative of the phase samples, which is analogous to frequency.

The formula for the frequency lock detect threshold value

(FLDT) is

























∆

round

Gain

FPFD

FLDT

where fR is the frequency of the active reference, R is the value of

the reference prescaler, and Δf is the maximum frequency

deviation of fR that is considered to indicate a frequency-locked

condition (Δf ≥ 0).

ABSOLUTE

VALUE

DIFFERENCER

DIGITAL

COMPARATOR

CONTROL LOGIC

UNLOCK

TIMER

LOCK

TIMER

FREQUENCY LOCK DETECT

THRESHOLD

LOOP

FREQUENCY

LOCK

DETECT

RESET

P-DIVIDER

CLOCK

PHASE

DETECTOR

SAMPLES

I/O

REGISTERS

Figure 30. Frequency Lock Detection

fR/R

fS/P

THRESHOLD

COMPARATOR

PHASE ERROR

MAGNITUDE

SAMPLES

LOCK

TIMER

(X = 3)

UNLOCK

TIMER

(Y = 1)

LOCKED

THRESHOLD

Figure 31. Lock/Unlock Detection Timing

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