AD9549APCBZ datasheet(17/76 Pages) AD

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AD9549

Rev. D | Page 17 of 76

THEORY OF OPERATION

DDS/DAC

FREQUENCY

TUNING

WORD

SLEW

LIMIT

PROG.

DIGITAL

LOOP

FILTER

PFD

÷R

FREQ

EST.

÷S

LOCK DETECT

2×

DIGITAL PLL CORE

HOLDOVER

CONTROL

LOGIC

LOW NOISE

CLOCK

MULTIPLIER

SYSCLK PORT

INPUT

REF

MONITOR

IRQ AND

STATUS

LOGIC

OOL AND LOR

REF_CNTRL

EXTERNAL

ANALOG

LOW-PASS

FILTER

DIGITAL

INTERFACE

HOLDOVER

SYSCLK

FDBK_IN

DAC_OUT

OUT

OUT_CMOS

S1 TO S4

REFB_IN

REFA_IN

REFSELECT

AMP

Figure 22. Detailed Block Diagram

OVERVIEW

The AD9549 provides a clocking output that is directly related

in phase and frequency to the selected (active) reference (REFA

or REFB) but has a phase noise spectrum primarily governed

by the system clock. A wide band of reference frequencies is

supported. Jitter existing on the active reference is greatly reduced

by a programmable digital filter in the digital phase-locked loop

(PLL), which is the core of this product. The AD9549 supports

both manual and automatic holdover. While in holdover, the

AD9549 continues to provide an output as long as the system

clock is maintained. The frequency of the output during hold-

over is an average of the steady state output frequency prior to

holdover.

Also offered are manual and automatic switchover modes for

changing between the two references, should one become suspect

or lost. A digitally controlled oscillator (DCO) is implemented

using a direct digital synthesizer (DDS) with an integrated output

digital-to-analog converter (DAC), clocked by the system clock.

A bypassable PLL-based frequency multiplier is present, enabling

use of an inexpensive, low frequency source for the system clock.

For best jitter performance, the system clock PLL should be

bypassed; and a low noise, high frequency system clock should be

provided directly. Sampling theory sets an upper bound for the

DDS output frequency at 50%

of fS (where fS is the DAC sample rate), but a practical limitation

of 40% of fS is generally recommended to allow for the selectivity

of the required off-chip reconstruction filter. The output signal

from the reconstruction filter is fed back to the AD9549, both

to complete the PLL and to be processed through the output

circuitry. The output circuitry includes HSTL and CMOS output

buffers, as well as a frequency doubler for designs that must

provide frequencies above the Nyquist level of the DDS.

The individual functional blocks are described in the following

sections.

DIGITAL PLL CORE (DPLLC)

The digital phase-locked loop core (DPLLC) includes the

frequency estimation block and the digital phase lock control

block driving the DDS.

The start of the DPLLC signal chain is the reference signal, fR,

which appears on REFA or REFB inputs. The frequency of this

signal can be divided by an integer factor of R via the feedforward

divider. The output of the feedforward divider is routed to the

phase/frequency detector (PFD). Therefore, the frequency at

the input to the PFD is given by

PFD =

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