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AD9549APCBZ 数据表(PDF) 48 Page - Analog Devices |
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AD9549APCBZ 数据表(HTML) 48 Page - Analog Devices |
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48 / 76 page  AD9549 Rev. D | Page 48 of 76 I/O REGISTER MAP All address and bit locations that are left blank in Table 13 are unused. Accessing reserved registers should be avoided. In cases where some of the bits in register are reserved, the user can rely on the default value in the I/O register map and write the same value back to the reserved bits in that register. Table 13. Addr (Hex) Type1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 BIt 2 Bit 1 Bit 0 Default (Hex) Serial port configuration and part identification 0x0000 Serial config. SDO active LSB first (buffered) Soft reset Long inst. Long inst. Soft reset LSB first (buffered) SDO active 0x18 0x0001 Reserved Reserved 0x0002 RO Part ID Part ID 0x82 0x0003 RO 0x09 0x0004 Serial options Read buffer register 0x00 0x0005 AC Register update 0x00 Power-down and reset 0x0010 Power- down and enable PD HSTL driver Enable CMOS driver Enable output doubler PD SYSCLK PLL PD REFA PD REFB Full PD Digital PD 0x00 0x0011 Reserved Reserved 0x0012 M, AC Reset History reset IRQ reset FPFD reset CPFD reset LF reset CCI reset DDS reset 0x00 0x0013 M PD fund DDS S-div/2 reset R-div/2 reset S-divider reset R-divider reset 0x00 System clock 0x0020 N-divider N-divider, Bits[4:0] 0x12 0x0021 Reserved Reserved 0x0022 PLL parameters VCO auto range 2× reference VCO range Charge pump current, Bits[1:0] 0x04 0x0023 PFD divider PFD divider, Bits[3:0] (relationship between SYSCLK and PFD clock) 0x05 DPLL 0x0100 M PLL control Reserved Single- tone mode Disable freq. estimator Enable freq. slew limiter Reserved Loop polarity Close loop 0x30 0x0101 R-divider R-divider, Bits[15:0] 0x00 0x0102 0x00 0x0103 Falling edge triggered Reserved R-divider/2 0x00 0x0104 S-divider S-divider, Bits[15:0] 0x00 0x0105 0x00 0x0106 Falling edge triggered Reserved S-divider/2 0x00 0x0107 M P-divider P-divider, Bits[4:0] 0x05 |
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