AD9549APCBZ datasheet(21/76 Pages) AD

21 / 76 page

AD9549

Rev. D | Page 21 of 76

In holdover mode, the AD9549 uses past tuning words when

the loop is closed to determine its output frequency. Therefore,

the loop must be successfully closed for holdover mode to work.

Switching in and out of holdover mode can be either automatic

or manual, depending on register settings.

Typically, the AD9549 operates in closed-loop mode. In closed-

loop mode, the FTW values come from the output of the digital

loop filter and vary with time. The DDS frequency is steered in

a manner similar to a conventional VCO-based PLL.

Note that in closed-loop mode, the DDS phase offset capability

is inoperative.

DAC Output

The output of the digital core of the DDS is a time series of

numbers representing a sinusoidal waveform. This series is

translated to an analog signal by means of a digital-to-analog

converter (DAC).

The DAC outputs its signal to two pins driven by a balanced

current source architecture (see the DAC output diagram in

Figure 26). The peak output current derives from the combi-

nation of two factors. The first is a reference current (IDAC_REF)

established at the DAC_RSET pin, and the second is a scale

factor programmed into the I/O register map.

SWITCH

CONTROL

CODE

IFS/2

AVDD3

AVSS

CURRENT

SWITCH

ARRAY

CURRENT

SWITCH

ARRAY

IOUT

IOUTB

Ω

IFS/2 + ICODE

IFS/2 – ICODE

IFS

Figure 26. DAC Output Pins

The value of IDAC_REF is set by connecting a resistor (RDAC_REF)

between the DAC_RSET pin and ground. The DAC_RSET pin

is internally connected to a virtual voltage reference of 1.2 V

nominal, so the reference current can be calculated by

REF

DAC

REF

DAC

Note that the recommended value of IDAC_REF is 120 μA, which

leads to a recommended value for RDAC_REF of 10 kΩ.

The scale factor consists of a 10-bit binary number (FSC)

programmed into the DAC full-scale current register (Address

0x040B and Address 0x040C) in the I/O register map. The full-

scale DAC output current (IDAC_FS) is given by













1024

192

FSC

REF

DAC

Using the recommended value of RDAC_REF, the full-scale DAC

output current can be set with 10-bit granularity over a range of

approximately 8.6 mA to 31.7 mA. The default value is 20 mA.

PHASE DETECTOR

Coarse Phase Detector

The coarse phase detector uses the DAC sample rate (fS) to

determine the edge timing deviation between the REF signal

and the feedback signal generated by the DDS. Hence, fS sets

the timing resolution of the coarse phase detector. At the

recommended rate of fS = 1 GHz, the coarse phase detector

spans a range of over 131 μs (sufficient to accommodate REF

signal frequencies as low as 8 kHz).

The phase gain of the coarse phase detector is controlled via the

I/O registers by means of two numeric entries. The first is a

3-bit, power-of-2 scale factor, PDS. The second is a 6-bit linear

scale factor, PDG.

(

)

PDG

PhaseGain

PDS

CPD













Fine Phase Detector

The fine phase detector operates on a divided down version

of fS as its sampling time base. The sample rate of the fine phase

detector is set using a 4-bit word (PFD_Div) in the I/O register

map (Register 0x0023) and is given by

)

(

Div

PFD

Rate

Sample

Detector

Phase

Fine

The default value of PFD_Div is 5, so for fS = 1 GHz, the default

sample rate of the fine phase detector is 50 MHz. The upper

bound on the maximum allowable input frequency to the phase

detector (fPFD[MAX]) is 49% of the sample rate, or

)

(

]

[

Div

PFD

MAX

PFD

Therefore, fPFD[MAX] is 25 MHz in the preceding example.

The fine phase detector uses a proprietary technique to

determine the phase deviation between the REF signal and

feedback signal.

The phase gain of the fine phase detector is controlled by

an 8-bit scale factor (FPFD_Gain) in the I/O register map

(Register 0x0404). The nominal (default) value of FPFD_Gain

is 200 and establishes the phase gain as

Gain

FPFD

PhaseGain

)

)(

(

10 ×

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