AD9549APCBZ datasheet(11/76 Pages) AD

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AD9549

Rev. D | Page 11 of 76

Pin No.

Input/

Output

Pin Type

Mnemonic

Description

20, 21

PFD_VRB,

PFD_VRT

These pins must be capacitively decoupled. See the Phase Detector Pin

Connections section for details.

Current set

resistor

PFD_RSET

Connect a 5 kΩ resistor from this pin to ground (see the Phase Detector Pin

Connections section).

Differential

input

SYSCLK

System Clock Input. The system clock input has internal dc biasing and should

always be ac-coupled, except when using a crystal. Single-ended 1.8 V CMOS

can also be used, but it may introduce a spur caused by an input duty cycle

that is not 50%. When using a crystal, tie the CLKMODESEL pin to AVSS, and

connect crystal directly to this pin and Pin 28.

Differential

input

SYSCLKB

Complementary System Clock. Complementary signal to the input provided

on Pin 27. Use a 0.01 μF capacitor to ground on this pin if the signal provided

on Pin 27 is single-ended.

LOOP_FILTER

System Clock Multiplier Loop Filter. When using the frequency multiplier to

drive the system clock, an external loop filter must be constructed and attached to

this pin. This pin should be pulled down to ground with a 1 kΩ resistor when

the system clock PLL is bypassed. See Figure 44 for a diagram of the system

clock PLL loop filter.

1.8 V CMOS

CLKMODESEL

Clock Mode Select. Set to GND when connecting a crystal to the system clock

input (Pin 27 and Pin 28). Pull up to 1.8 V when using either an oscillator or an

external clock source. This pin can be left floating when the system clock PLL is

bypassed. (See the SYSCLK Inputs section for details on the use of this pin.)

33, 39, 43, 52

GND

AVSS

Analog Ground. Connect to ground.

1.8 V HSTL

OUTB

Complementary HSTL Output. See the Specifications and Primary 1.8 V

Differential HSTL Driver sections for details.

1.8 V HSTL

OUT

HSTL Output. See the Specifications and Primary 1.8 V Differential HSTL Driver

sections for details.

Power

AVDD3

Analog Supply for CMOS Output Driver. This pin is normally 3.3 V but can be

1.8 V. This pin should be powered even if the CMOS driver is not used. See the

Power Supply Partitioning section for power supply partitioning.

3.3 V CMOS

OUT_CMOS

CMOS Output. See the Specifications and the Output Clock Drivers and 2×

Frequency Multiplier sections. This pin is 1.8 V CMOS if Pin 37 is set to 1.8 V.

Differential

input

FDBK_INB

Complementary Feedback Input. In standard operating mode, this pin is

connected to the filtered DAC_OUTB output. This internally biased input is

typically ac-coupled, and when configured as such, can accept any differential

signal whose single-ended swing is at least 400 mV.

Differential

input

FDBK_IN

Feedback Input. In standard operating mode, this pin is connected to the

filtered DAC_OUT output.

Current set

resistor

DAC_RSET

DAC Output Current Setting Resistor. Connect a resistor (usually 10 kΩ) from

this pin to GND. See the DAC Output section.

Differential

output

DAC_OUT

DAC Output. This signal should be filtered and sent back on chip through

FDBK_IN input. This pin has an internal 50 Ω pull-down resistor.

Differential

output

DAC_OUTB

Complementary DAC Output. This signal should be filtered and sent back on

chip through FDBK_INB input. This pin has an internal 50 Ω pull-down resistor.

I/O

3.3 V CMOS

REFSELECT

Reference Select Input. In manual mode, the REFSELECT pin operates as a high

impedance input pin; and in automatic mode, it operates as a low impedance

output pin. Logic 0 (low) indicates/selects REFA. Logic 1 (high) indicates/selects

REFB. There is no internal pull-up/pull-down resistor on this pin.

I/O

3.3 V CMOS

HOLDOVER

Holdover (Active High). In manual holdover mode, this pin is used to force the

AD9549 into holdover mode. In automatic holdover mode, it indicates

holdover status. There is no internal pull-up/pull-down resistor on this pin.

3.3 V CMOS

PWRDOWN

Power-Down. When this active high pin is asserted, the device becomes

inactive and enters the full power-down state. This pin has an internal 50 kΩ

pull-down resistor.

3.3 V CMOS

RESET

Chip Reset. When this active high pin is asserted, the chip goes into reset. Note

that on power-up, it is recommended that the user assert a high to low edge

after the power supplies reach a threshold and stabilize. This pin has an

internal 50 kΩ pull-down resistor.

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