AD9549APCBZ datasheet(14/76 Pages) AD

部件名	AD9549APCBZ

功能描述	Dual Input Network Clock Generator/Synchronizer

PDF	76 Pages

Scroll/Zoom	100%

制造商	AD [Analog Devices]

网页	http://www.analog.com

标志

14 / 76 page

AD9549

Rev. D | Page 14 of 76

SYSTEM CLOCK PLL INPUT FREQUENCY (MHz)

2.0

1.5

1.0

0.5

Figure 9. 12 kHz to 20 MHz RMS Jitter vs. System Clock PLL Input Frequency,

SYSCLK = 1 GHz, fREF = 19.44 MHz, fOUT = 155.52 MHz

100

10k

100k

10M

100M

FREQUENCY OFFSET (Hz)

–70

–80

–90

–100

–110

–120

–130

–140

–150

RMS JITTER (12kHz TO 20MHz): 1.26ps

RMS JITTER (50kHz TO 80MHz): 1.30ps

Figure 10. Additive Phase Noise at HSTL Output Driver, SYSCLK = 1 GHz

(SYSCLK PLL Enabled and Driven by a 25 MHz Fox Crystal Oscillator),

fREF = 19.44 MHz, fOUT = 155.52 MHz, DPLL Loop BW = 1 kHz

100

10k

100k

10M

FREQUENCY OFFSET (Hz)

–70

–80

–90

–100

–110

–120

–130

–140

–150

RMS JITTER (12kHz TO 20MHz): 4.2ps

Figure 11. Additive Phase Noise at HSTL Output Driver, SYSCLK = 500 MHz

(SYSCLK PLL Disabled), fREF = 10.24 MHz, fOUT = 20.48 MHz,

DPLL Loop BW = 1 kHz

AD9549APCBZ 数据表(PDF) 14 Page - Analog Devices

AD9549APCBZ 数据表(HTML) 14 Page - Analog Devices

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