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AD9549APCBZ 数据表(PDF) 23 Page - Analog Devices |
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AD9549APCBZ 数据表(HTML) 23 Page - Analog Devices |
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23 / 76 page ![]() AD9549 Rev. D | Page 23 of 76 The three coefficients are implemented as digital elements, necessitating quantized values. Determination of the programmed coefficient values in this context follows. The quantized α coefficient is composed of three factors, where α0, α1, and α2 are the programmed values for the α coefficient. ( )( )2 1 α α 0 QUANTIZED α α − = 2 2 2048 The boundary values for each are 0 ≤ α0 ≤ 4095, 0 ≤ α1 ≤ 22, and 0 ≤ α2 ≤ 7. The optimal values of α0, α1, and α2 are = 4095 2048 log ceil , 22 min , 0 max 2 α α1 − α + α = 11 4095 log floor , 7 min , 0 max 2 1 2 α ( ) { } [ ] 11 2 round , 4095 min , 0 max + − × = 1 2 α α 0 α α The magnitude of the quantized β coefficient is composed of two factors ( ) ( )) 15 ( 2 + − = 1 β 0 QUANTIZED β β where β0 and β1 are the programmed values for the β coefficient. The boundary values for each are 0 ≤ β0 ≤ 4095 and 0 ≤ β1 ≤ 7. The optimal values of β0 and β1 are − = 15 4095 log floor , 7 min , 0 max 2 β β1 ( ) { } [ ] 15 2 round , 4095 min , 0 max + × = 1 β 0 β β The magnitude of the quantized γ coefficient is composed of two factors. ( ) ( )) 15 ( 2 + − = 1 γ 0 QUANTIZED γ γ where γ0 and γ1 are the programmed values for the γ coefficient. The boundary values for each are 0 ≤ γ0 ≤ 4095 and 0 ≤ γ1 ≤ 7. The optimal values of γ0 and γ1 are − γ = γ 15 4095 log floor , 7 min , 0 max 2 1 ( ) { } [ ] 15 2 round , 4095 min , 0 max + γ × γ = γ 1 0 The min(), max(), floor(), ceil() and round() functions are defined as follows: • The function min(x1, x2, … xn) chooses the smallest value in the list of arguments. • The function max(x1, x2, … xn) chooses the largest value in the list of arguments. • The function ceil(x) increases x to the next higher integer if x is not an integer; otherwise, x is unchanged. • The function floor(x) reduces x to the next lower integer if x is not an integer; otherwise, x is unchanged. • The function round(x) rounds x to the nearest integer. To demonstrate the wide programmable range of the loop filter bandwidth, consider the following design example. The system clock frequency (fS) is 1 GHz, the input reference frequency (fR) is 19.44 MHz, the DDS output frequency (fDDS) is 155.52 MHz, and the required phase margin (Φ) is 45°. fR is within the nominal bandwidth of the phase detector (25 MHz), and fDDS/fR is an integer (8), so the prescaler is not required. Therefore, R = 1 and S = 8 can be used for the feedforward and feedback dividers, respectively. Note that if fDDS/fR is a noninteger, then R and S must be chosen such that S/R = fDDS/fR with S and R both constrained to integer values. For example, if fR = 10 MHz and fDDS = 155.52 MHz, then the optimal choice for S and R is 1944 and 125, respectively. The open-loop bandwidth range under the defined conditions spans 9.5 Hz to 257.5 kHz. The wide dynamic range of the loop filter coefficients allows for programming of any open-loop bandwidth within this range under these conditions. The resulting closed-loop bandwidth range under the same conditions is approximately 12 Hz to 359 kHz. The resulting loop filter coefficients for the upper loop bandwidth, along with the necessary programming values, are shown as follows: α = 4322509.4784981 α0 = 2111 (0x83F) α1 = 22 (0x16) α2 = 0 (0x00) β = −0.10354689386232 β0 = 3393 (0xD41) β1 = 0 (0x00) γ0 = 4095 (0xFFF) γ = −0.12499215775201 γ1 = 0 (0x00) |
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