AD9549APCBZ datasheet(28/76 Pages) AD

28 / 76 page

AD9549

Rev. D | Page 28 of 76

Use of Line Card Mode to Eliminate Runt Pulses

When two references are not in exact phase alignment and

a transition is made from one to the other, it is possible that an

extra pulse may be generated. This depends on the relative edge

placement of the two references and the point in time that a switch-

over is initiated. To eliminate the extra pulse problem, an enable

line card mode bit is provided (Register 0x01C1, Bit 4). The line

card mode logic is shown in Figure 34. When the enable line card

bit is set to 0, reference switchover occurs on command without

consideration of the relative edge placement of the references.

This means that there is the possibility of an extra pulse. However,

when this bit is set to 1, the timing of the reference switchover is

executed conditionally, as shown in Figure 35.

ENABLE

LINE CARD

MODE

REF IN

FROM

REFERENCE

SELECTION

LOGIC

REFA_IN

REFB_IN

SELECTED

REFERENCE

Figure 34. Reference Switchover Control Logic

Note that when the line card mode is enabled, the rising edges

of the alternate reference are used to clock a latch. The latch

holds off the actual transition until the next rising edge of the

alternate reference.

Figure 35 shows a timing diagram that demonstrates the difference

between reference switchover with the line card mode enabled

and disabled. If enabled, when the reference switchover logic is

given the command to switch to the alternate reference, an actual

transition does not occur until the next rising edge of the alter-

nate reference. This action eliminates the spurious pulse that can

occur when the line card mode is disabled.

REF SELECTION STALLED UNTIL

NEXT RISING EDGE OF REFB

SELECT REFB

SELECT

REFA

REFA IN

REFB IN

FROM REFERENCE

SELECTION LOGIC

REF IN

DISABLED

ENABLED

LINE CARD

MODE

Figure 35. Reference Switchover Timing

Effect of Reference Input Switchover on Output Clock

This section covers the transient behavior of the AD9549

during a clock switchover event. This is also applicable when

the AD9549 leaves holdover and reverts to being locked to

a reference input. There is no phase disturbance entering

holdover mode.

Switching reference inputs with different phases causes a transient

frequency disturbance at the output of the PLL. The magnitude

of this disturbance depends on the frequency of the reference

inputs, the magnitude of the phase offset between the two

references, and the digital PLL loop bandwidth.

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

TIME (s)

REFERENCE SWITCHING:

10ns DELTA @ 0.2Hz BANDWIDTH, 70° PHASE MARGIN

Figure 36. Output Phase vs. Time for a Reference Switchover

Figure 36 shows the output phase as a function of time for a

reference switchover event. In this example, Reference A and

Reference B are both 30.72 MHz and have a 10 ns (102°) phase

offset. The digital PLL loop bandwidth is 0.2 Hz.

The frequency disturbance is the slope of the shift in Figure 36.

The maximum slope is 4.75 divisions in one second of time,

which gives the following transient frequency error, assuming

that the output is also 30.72 MHz:

292

105

divs

∆

The maximum frequency error for this transient is

ppm

0095

MHz

292

cyError

MaxFrequen

To apply this to a general case, the designer should calculate the

maximum time difference between two reference edges that are

180° apart. The preceding calculation of the slope, m, becomes

0.5 Hz, not 0.292 Hz, for a phase shift of 180°. Next, the frequency

error must be scaled for the loop bandwidth used. The frequency

error for 1 kHz is 5000× greater than for 0.2 Hz, so the peak

frequency error for the preceding example of 102° is 47.4 ppm,

and 81.3 ppm for a 180° phase error between the reference inputs.

AD9549APCBZ 数据表(PDF) 28 Page - Analog Devices

AD9549APCBZ 数据表(HTML) 28 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

数据表下载