CS49310 datasheet(67/86 Pages) CIRRUS

67 / 86 page

CS49300 Family DSP

DS339PP4

HARDWARE CONFIGURATION

After

download

soft

reset,

and

before

kickstarting the application (please see the Audio

Manager in the Application Messaging Section of

any Application Code User’s Guide for more

information on kickstarting), the host has the

option

changing

the

default

hardware

configuration. Hardware configuration messages

are used to physically reconfigure the hardware of

the audio decoder, as in enabling or disabling

address checking for the serial communication

port. Hardware configuration messages are also

used to initialize the data type (i.e., PCM or

compressed) and format (e.g., I2S, left justified,

etc.) for digital data inputs, as well as the data

format and clocking options for the digital output

port.

In general, the hardware configuration can only be

changed immediately after download or after soft

reset. However, some applications provide the

capability to change the input ports without

affecting other hardware configurations after

sending a special Application Restart message

(please see the Audio Manager in any Application

Code User’s Guide to determine whether the

Application Restart message is supported). Section

11.4 at the end of this chapter will describe how to

construct a hardware configuration message.

10. DIGITAL INPUT & OUTPUT

The CS493XX supports a wide variety of data

input and output mechanisms through various input

and output ports. Hardware availability is entirely

dependent on whether the software application

code being used supports the required mode. This

data sheet presents most of the modes available

with the CS493XX hardware. This does not mean

that all of the modes are available with any

particular

piece

application

code.

The

application code user’s guide for the particular

code being used should be referenced to determine

if a particular mode is supported. In addition if a

particular mode is desired that is not presented,

please contact your sales representative as to its

availability.

10.1. Digital Audio Formats

This subsection will describe some common audio

formats that the CS493XX supports. It should be

noted that the input ports use up to 24-bit PCM

resolution and 16-bit compressed data word

lengths. The output port of the CS493XX provides

up to 24-bit PCM resolution.

10.1.1.I2S

Figure 43, "I2S Format" on page 68 shows the I2S

format. For I2S, data is presented most significant

bit first, one SCLK delay after the transition of

LRCLK and is valid on the rising edge of SCLK.

For the I2S format, the left subframe is presented

when LRCLK is low and the right subframe is

presented when LRCLK is high. SCLK is required

to run at a frequency of 48Fs or greater on the input

ports.

10.1.2.Left Justified

Figure 44 shows the left justified format with a

rising edge SCCLK. Data is presented most

significant bit first on the first SCLK after an

LRCLK transition and is valid on the rising edge of

SCLK. For the left justified format, the left

subframe is presented when LRCLK is high and the

right subframe is presented when LRCLK is low.

The left justified format can also be programmed

for data to be valid on the falling edge of SCLK.

SCLK is required to run at a frequency of 48Fs or

greater on the input ports.

10.1.3.Multichannel

Figure 45 shows the multichannel format. In this

format up to 6 channels of audio are presented on

one data line with M bits per channel. Channels 0,

2, and 4 are presented while the LRCLK is high and

channels 1, 3, 5 are presented while the LRCLK is

low. Data is valid on the rising edge of SCLK and

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