CS49310 datasheet(32/86 Pages) CIRRUS

32 / 86 page

CS49300 Family DSP

DS339PP4

scheme is shown in the typical connection

diagrams.

4.3. Ground

For two layer applications, care should be taken to

have sufficient ground between the DSP and parts

in which it will be interfacing (DACs, ADCs, DIR,

microcontrollers, external memory etc). If there is

not sufficient ground, a potential will be seen

between the ground reference of the DSP and the

interface parts and the noise margin will be

significantly

reduced

potentially

causing

communication or data integrity problems.

4.4. Pads

The CS493XX incorporate 3.3V tolerant pads. This

means that while the CS493XX power supplies

require 2.5 volts, 3.3 volt signals can be applied to

the inputs without damaging the part.

CLOCKING

The CS493XX clock manager incorporates a

programmable phase locked loop (PLL) clock

synthesizer. The PLL takes an input reference

clock and produces all the internal clocks required

to run the internal DSP and to provide master mode

timing to the audio input/output peripherals. The

clock manager also includes a 33-bit system time

clock

(STC)

support

audio

and

video

synchronization.

The PLL can be internally bypassed by connecting

the CLKSEL pin to VD. This connection

multiplexes the CLKIN pin directly to the DSP

clock. Care should be taken to note the minimum

CLKIN requirements when bypassing the PLL.

The PLL reference clock has three possible sources

that are routed through a multiplexer controlled by

the DSP: SCLKN2, SCLKN1, and CLKIN.

Typically, in audio/video environments like set-top

boxes, the CLKIN pin is connected to 27 MHz. In

other scenarios such as an A/V receiver design, the

PLL can be clocked through the CLKIN pin with

even multiples of the desired sampling rate or with

an already available clock source. Typically a

12.288 MHz CLKIN is used in this scenario so that

the same oscillator can be used for the DSP and

ADC.

The clock manager is controlled by the DSP

application software. The software user’s guide for

the application code being used should be

referenced for what CLKIN input frequency is

supported.

CONTROL

Control of the CS493XX can be accomplished

through one of four methods. The CS493XX

supports I2C® and SPI serial communication. In

addition the CS493XX supports both a Motorola

and Intel byte wide parallel host control mode.

Only one of the four communication modes can be

selected for control. The states of the RD, WR, and

PSEL pins are sampled at the rising edge of RESET

to determine the interface type as shown in Table 2.

Whichever host communication mode is used, host

control of the CS493XX is handled through the

application

software

running

the

DSP.

Configuration and control of the CS493XX

decoder and its peripherals are indirectly executed

through a messaging protocol supported by the

downloaded application code. In other words

successful

communication

can

only

accomplished by following the low level hardware

communication format and high level messaging

protocol. The specifications of the messaging

protocol can be found in any of the software user’s

guides.

(Pin 5)

(Pin 4)

PSEL

(Pin 19)

Host Interface Mode

8-bit Motorola®

8-bit Intel®

Serial I2C®

Serial SPI

Table 2. Host Modes

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