CS49310 datasheet(70/86 Pages) CIRRUS

70 / 86 page

CS49300 Family DSP

DS339PP4

During delivery of a block of data the FIFO

threshold should not be checked. In other words the

FIFO indicators are level sensitive and indicate that

a block can be delivered when they are low. They

may return high during the data delivery. When this

happens there is still room for the remaining bytes

of the block.

The PCM data input register (PCMDAT) receives

bytes of data when the host interface writes to

address 10b (A1 high, A0 low). The MFC bit in the

Host Control Register is an indicator of the PCM

FIFO level. The MFC bit remains low until the

FIFO threshold has been reached.

The PCMRST bit of the CONTROL register

provides

absolute

software/hardware

synchronization by initializing the input channel to

uniquely recognize the first write to the byte-wide

PCMDATA port. Toggling PCMRST high and low

informs the DSP that the next sample read from the

PCMDATA port is the first sample of the left

channel. In this fashion, the CS493XX can

translate successive byte writes into a variable

number of channels with a variable PCM sample

size. In the most simple case, the CS493XX can

receive stereo 8-bit PCM one byte at a time with the

internal DSP assigning the first 8-bit write (after

PCMRST) to the left channel and the second 8-bit

write to the right channel. For 24-bit PCM, it

assigns the first three 8-bit writes (after PCMRST)

to the left channel and the next three writes to the

right channel. Before starting PCM transfer, or to

initiate a new PCM transfer, the PCMRST bit must

be toggled as described above to insure data

integrity.

Data must be delivered to the CS493XX in blocks

of data. The block size is set through a hardware

configuration message. Before each block is

delivered, the host should check the MFC bit. If the

MFC bit is low, then the host can deliver a block of

data one byte at a time. If the MFC bit is high, no

more data should be sent to the CS493XX. Once

the MFC bit has gone low again, the host may send

another block of PCM audio data. The MFC bit is

FIFO level sensitive. In other words, it may change

during the transfer of a block. The host should

complete the block transfer and ignore the MFC bit

until the block transfer is complete.

10.4.2.Parallel Delivery with Serial Control

When using I2C or SPI control, bytewide delivery

data

can

still

achieved

using

SCLKN2(CMPCLK) and GPIO[8:0]. In this mode

the bytewide parallel data is clocked into the part

on the transition of CMPCLK.

In this mode CMPREQ can be used as the FIFO

threshold indicator. When CMPREQ is low it

means that the CS493XX can receive another block

of data.

10.5. Digital Audio Output Port

The Digital Audio Output port, or DAO, is the port

used for digital output from the DSP. Table 15

shows the signals associated with the DAO. As

with the input ports the clocks and data are fully

configurable via hardware configuration.

MCLK is the master clock and is firmware

configurable to be either an input or an output. If

MCLK is to be used as an output, the internal PLL

must be used. As an output MCLK can be

Pin Name

Pin Description

Pin Number

AUDATA3,

XMT958

Serial Data Out

IEC60958 Transmitter

AUDATA2

Serial Data Out

AUDATA1

Serial Data Out

AUDATA0

Serial Data Out

LRCLK

Frame Clock

SCLK

Serial Bit Clock

MCLK

Master Clock

Table 15. Digital Audio Output Port

CS49310 数据表(PDF) 70 Page - Cirrus Logic

CS49310 数据表(HTML) 70 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

数据表下载

链接网址

CS49310 数据表(PDF) 70 Page - Cirrus Logic

CS49310 数据表(HTML) 70 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

数据表 下载

链接网址

数据表下载