CS49310 datasheet(34/86 Pages) CIRRUS

34 / 86 page

CS49300 Family DSP

DS339PP4

write. Once again it is crucial that the serial

clock transitions from high to low on the last bit

of the last byte before chip select is raised, or a

loss of data will occur.

The same write routine could be used to send a

single byte, message or an entire application code

image. From a hardware perspective, it makes no

difference whether communication is by byte or

multiple bytes of any length as long as the correct

hardware protocol is followed.

6.1.1.2.Reading in SPI

A read operation is necessary when the CS493XX

signals that it has data to be read. The CS493XX

does this by dropping its interrupt request line

(INTREQ) low. When reading from the device in

SPI, the same protocol will be used whether

reading a single byte or multiple bytes. The

examples shown in this document can be expanded

to fit any read situation. Figure 20, "SPI Read Flow

Diagram" on page 34 shows a typical read

sequence:

The following is a detailed description of an SPI

read sequence with the CS493XX.

1) An SPI read transaction is initiated by the

CS493XX dropping INTREQ, signaling that it

has data to be read.

2) The host responds by driving chip select (CS)

low.

3) This is followed by a 7-bit address and the

read/write bit set high for a read. The address

for the CS493XX defaults to 0000000b. It is

necessary to clock this address in prior to any

transfer

order

for

the

CS493XX

acknowledge the read. In other words a byte of

0x01 should be clocked into the device

preceding any read. The 0x01 byte represents

the 7 bit address 0000000b, and the least

significant bit set to 1 to designate a read.

4) After the falling edge of the serial control clock

(SCCLK) for the read/write bit, the data is

ready to be clocked out on the control data out

pin (CDOUT). Data clocked out by the host is

valid on the rising edge of SCCLK and data

transitions occur on the falling edge of SCCLK.

The serial clock should be default low so that

eight transitions from low to high to low will

occur for each byte.

5) If INTREQ is still low, another byte should be

clocked out of the CS493XX. Please see the

discussion below for a complete description of

INTREQ behavior.

6) When INTREQ has risen, the chip select line of

the CS493XX should be raised to end the read

Figure 20. SPI Read Flow Diagram

CS (LOW)

WRITE ADDRESS BYTE

SET TO 1 FOR READ

READ DATA BYTE

INTREQ STILL LOW?

CS (HIGH)

WITH MODE BIT

YES

INTREQ LOW?

YES

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