CS49310 datasheet(41/86 Pages) CIRRUS

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CS49300 Family DSP

DS339PP4

for the data bit D0 (SCCLK N-1), but it can go low

at the rising edge of SCCLK for the NACK bit

(SCCLK N) if an unsolicited message has arrived.

If no unsolicited messages arrive, the INTREQ pin

will remain high after rising.

INTREQ behavior for SPI communication is

illustrated in Figure 21, "SPI Timing" on page 36.

When using SPI communication, the INTREQ pin

will remain low until the rising edge of SCCLK for

the data bit D1 (SCCLK N-1), but it can go low at

the rising edge of SCCLK for data bit D0 (SCCLK

N) if an unsolicited message has arrived. If no

unsolicited messages arrive, the INTREQ pin will

remain high after rising.

Ideally, the host will sample INTREQ on the

falling edge of SCCLK number N-1 of the final

byte of each read response message. If INTREQ is

sampled high, the host should conclude the current

read cycle using the stop condition defined for the

communication mode chosen. The host should then

begin a new read cycle complete with the

appropriate start condition and the chip address. If

INTREQ is sampled low, the host should continue

reading the next message from the CS493XX

without ending the current read cycle.

When using automated communication ports,

however, the host is often limited to sampling the

status of INTREQ after an entire byte has been

transferred. In this situation a low-high-low

transition (case 3) would be missed and the host

will see a constantly low INTREQ pin. Since the

host should read from the CS493XX until it detects

that INTREQ has gone high, this condition will be

treated as a multiple-message read (more than one

read response is provided by the CS493XX). Under

these conditions a single byte of 0x00 will be read

out before the unsolicited message.

The length of every read response is defined in the

user’s manual for each piece of application code.

Thus, the host should know how many bytes to

expect based on the first byte (the OPCODE) of a

read response message. It is guaranteed that no read

responses will begin with 0x00, which means that a

NULL byte (0x00) detected in the OPCODE

position of a read response message should be

discarded. Please see an Application Code User’s

Guide for an explanation of the OPCODE.

It is important that the host be aware of the

presence of NULL bytes, or the communication

channel could become corrupted.

When case (3) occurs and the host issues a stop

condition before starting a new read cycle, the first

byte of the unsolicited message is loaded directly

into the shift register and 0x00 is never seen.

Alternatively, if case (3) occurs and the host

continues to read from the CS493XX without a

stop condition (a multiple message read), the 0x00

byte must be shifted out of the CS493XX before

the first byte of the unsolicited message can be

read.

In other words, if a system can only sample

INTREQ after an entire byte transfer the following

routine should be used if INTREQ is low after the

last byte of the message being read:

1) Read one byte

2) If the byte = 0x00 discard it and skip to step 3.

If the byte != 0x00 then it is the OPCODE for

the next message. For this case skip to step 4.

3) Read one more byte. This is the OPCODE for

the next message.

4) Read the rest of the message as indicated in the

previous sections.

6.2. Parallel Host Communication

The parallel host communication modes of the

CS493XX provide an 8-bit interface to the DSP.

An Intel-style parallel mode and a Motorola-style

parallel mode are supported. The host interface is

implemented using four communication registers

within the CS493XX as shown in Table 5, “Parallel

Input/Output Registers,” on page 42.

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