CS49310 datasheet(14/86 Pages) CIRRUS

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CS49300 Family DSP

DS339PP4

1.10.

Switching Characteristics — I2C® Control Port

(TA = 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Notes:. 1. The specification fscl indicates the maximum speed of the hardware. The system designer should be

aware that the actual maximum speed of the communication port may be limited by the software. The

relevant application code user’s manual should be consulted for the software speed limitations.

2. Data must be held for sufficient time to bridge the 300-ns transition time of SCCLK. This hold time is by

design and not tested.

3. This rise time is

shorter than that recommended by the I2C specifications. For more information, see

Section 6.1, “Serial Communication” on page 33.

4. INTREQ goes high only if there is no data to be read from the DSP at the rising edge of SCCLK for the

last data bit of the last byte of data during a read operation as shown.

5. If INTREQ goes high as indicated in Note 8, then INTREQ is guaranteed to remain high until the next

rising edge of SCCLK. If there is more data to be read at this time, INTREQ goes active low again. Treat

this condition as a new read transaction. Send a new start condition followed by the 7-bit address and

the R/W bit (set to 1 for a read). This time is by design and is not tested.

6. With a 4.7k Ohm pull-up resistor this value is typically 215ns. As this pin is open drain adjusting the pull

up value will affect the rise time.

7. This time is by design and not tested.

Parameter

Symbol

Min

Max

Units

SCCLK clock frequency

(Note 1)

fscl

400

kHz

Bus free time between transmissions

tbuf

4.7

µs

Start-condition hold time (prior to first clock pulse)

thdst

4.0

µs

Clock low time

tlow

1.2

µs

Clock high time

thigh

1.0

µs

SCDIO setup time to SCCLK rising

tsud

250

SCDIO hold time from SCCLK falling

(Note 2)

thdd

µs

Rise time of SCCLK

(Note 3), (Note 7)

Fall time of SCCLK

(Note 7)

300

Time from SCCLK falling to CS493XX ACK

tsca

Time from SCCLK falling to SCDIO valid during read operation

tscsdv

Time from SCCLK rising to INTREQ rising

(Note 4)

tscrh

200

Hold time for INTREQ from SCCLK rising

(Note 5)

tscrl

0ns

Rise time for INTREQ

(Note 6)

trr

Setup time for stop condition

tsusp

4.7

µs

CS49310 数据表(PDF) 14 Page - Cirrus Logic

CS49310 数据表(HTML) 14 Page - Cirrus Logic

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