CS49310 datasheet(75/86 Pages) CIRRUS

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CS49300 Family DSP

DS339PP4

11.2.1. Input Configuration Considerations

1) 24-bit PCM input requires at least 24 SCLKS

per sub-frame. The DSP always uses 24-bit

resolution for PCM input. Systems having less

than 24-bit resolution will not have a problem

as the extra bits taken by the DSP will be under

the noise floor of the input signal for left

justified and I2S formats. For compressed

input, data is always taken in 16 bit word

lengths.

2) If the clocks to the audio ports are known to be

corrupted, such as when a S/PDIF receiver goes

out of lock, the DSP should undergo an

application restart (if applicable), soft reset or

hard reset. All three actions will result in the

input FIFO being reset. Failure to do so may

result in corrupted data being latched into the

input FIFO and may result in corrupted data

being heard on the outputs. This is not an issue

when compressed data is being delivered, as it

has sync words embedded in the stream which

the DSP can lock to, but only when PCM data

is being delivered. Certain application codes

that are capable of processing PCM may now

have

special

feature

called

“PCM

Robustness” which does alleviate the above

problem, however you should still follow the

above recommendation.

PCM - Left Justified 24-bit

Multichannel PCM (6 Channel)

- Left Justified 20-bit

(for Post-Processing Codes that can

accept 6 channels on one line like

THX Surround EX application code)

0x800217

0x8080FF

0x80021A

0x8080FF

0x800117

0x003CC0

0x80011A

0x0018C0

PCM - Left Justified 24-bit

Multichannel PCM (2 Channel)

- Left Justified 20-bit

(used only by special post-processing

application codes)

0x800217

0x8080FF

0x80021A

0x8080FF

0x800117

0x0014C0

0x80011A

0x0018C0

PCM - Left Justified 24-bit

Multichannel PCM (4 Channel)

- Left Justified 20-bit

(used only by special post-processing

application codes)

0x800217

0x8080FF

0x80021A

0x8080FF

0x800117

0x0028C0

0x80011A

0x0018C0

C Value

SCLK Polarity (Both CDI &

DAI Port)

Hex

Message

(default)

Data Clocked in on Rising

Edge

0x800217

0xFFFFDF

0x80021A

0xFFFFDF

Data Clocked in on Falling

Edge

0x800117

0x000020

0x80011A

0x000020

Table 20. Input SCLK Polarity Configuration

(Input Parameter C)

B Value

Data Format

Hex

Message

Table 19. Input Data Format Configuration

(Input Parameter B) (Continued)

D Value

FIFO Size & Blocksize (no

default - only applicable to

parallel delivery modes)

Hex

Message

Compressed FIFO B Size -

6kbyte

Blocksize - up to 2kbyte

0x800014

0x280D00

PCM FIFO C Size - 6kbyte

Blocksize - up to 2kbyte

0x800014

0x820300

Table 21. Input FIFO Setup Configuration

(Input Parameter D)

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