CS49310 datasheet(42/86 Pages) CIRRUS

42 / 86 page

CS49300 Family DSP

DS339PP4

Host Message (HOSTMSG) Register, A[1:0] = 00b

HOSTMSG7–0

Host data to and from the DSP. A read or write of this register operates handshake bits between

the internal DSP and the external host. This register typically passes multibyte messages car-

rying microcode, control, and configuration data. HOSTMSG is physically implemented as two

independent registers for input and output (read and write).

Host Control (CONTROL) Register, A[1:0] = 01b

Reserved

Always write a 0 for future compatibility.

CMPRST

When set, initializes the CMPDATA compressed data input channel. Writing a one to this bit

holds the port in reset. Writing zero enables the port. This bit must be low for normal operation.

(Write only)

PCMRST

When set, initializes the PCMDATA linear PCM input channel. Writing a one to this bit holds the

port in reset. Writing zero enables the port. This bit must be low for normal operation. (Write

only)

MFC

When high, indicates that the PCMDATA input buffer is almost full. (read only)

MFB

When high, indicates that the CMPDATA input buffer is almost full. (read only)

HINBSY

Set when the host writes to HOSTMSG. Cleared when the DSP reads data from the HOSTMSG

DSP. (Read only)

HOUTRDY

Set when the DSP writes to the HOSTMSG register. Cleared when the host reads data from

the HOSTMSG register. The DSP reads this bit to determine if the last DSP output byte has

been read by the host. (read only)

Reserved

Always write a 0 for future compatibility.

PCM Data Input (PCMDATA) Register, A[1:0] = 10b

PCMDATA7–0

The host writes PCM data to the DSP input buffer at this address. (Write only)

Compressed Data Input (CMPDATA) Register, A[1:0] = 11b

CMPDATA7–0

The host writes compressed data to the DSP input buffer at this address. (Write only)

765

4321

HOSTMSG7

HOSTMSG6

HOSTMSG5

HOSTMSG4

HOSTMSG3

HOSTMSG2

HOSTMSG1

HOSTMSG0

765

4321

Reserved

CMPRST

PCMRST

MFC

MFB

HINBSY

HOUTRDY

Reserved

765

4321

PCMDATA7

PCMDATA6

PCMDATA5

PCMDATA4

PCMDATA3

PCMDATA2

PCMDATA1

PCMDATA0

765

4321

CMPDATA7

CMPDATA6

CMPDATA5

CMPDATA4

CMPDATA3

CMPDATA2

CMPDATA1

CMPDATA0

Table 5. Parallel Input/Output Registers

CS49310 数据表(PDF) 42 Page - Cirrus Logic

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