CS49310 datasheet(83/86 Pages) CIRRUS

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CS49300 Family DSP

DS339PP4

MCLK—Audio Master Clock: Pin 44

Bidirectional master audio clock. MCLK can be an output from the CS493XX that provides an

oversampled audio-output clock at either 128 Fs, 256 Fs, or 512 Fs. MCLK can be an input at

128 Fs, 256 Fs, 384 Fs, or 512 Fs. MCLK is used to derive SCLK and LRCLK when SCLK

and LRCLK are driven by the CS493XX. BIDIRECTIONAL - Default: INPUT

SCLK—Audio Output Bit Clock: Pin 43

Bidirectional digital-audio output bit clock. SCLK can be an output that is derived from MCLK

to provide 32 Fs, 64 Fs, 128 Fs, 256 Fs, or 512 Fs, depending on the MCLK rate and the

digital-output configuration. SCLK can also be an input and must be at least 48Fs or greater.

As an input, SCLK is independent of MCLK. BIDIRECTIONAL - Default: INPUT

LRCLK—Audio Output Sample Rate Clock: Pin 42

Bidirectional digital-audio output-sample-rate clock. LRCLK can be an output that is divided

from MCLK to provide the output sample rate depending on the output configuration. LRCLK

can also be an input. As an input LRCLK is independent of MCLK.

BIDIRECTIONAL - Default: INPUT

AUDATA3,XMT958—SPDIF Transmitter Output, Digital Audio Output 3: Pin 3

CMOS level output that contains a biphase-mark encoded (S/PDIF) or I2S or Left Justified

digital audio data which is capable of carrying two channels of PCM digital audio or an

IEC61937 compressed-data interface.

Note: Outputting of IEC61937 is only available for certain broadcast-based application codes which run on

the CS4931X family or CS49330 device.

This output typically connects to the input of an RS-422 transmitter or to the input of an optical

transmitter. OUTPUT

SCLKN1, STCCLK2—PCM Audio Input Bit Clock: Pin 25

Bidirectional digital-audio bit clock that is an output in master mode and an input in slave

mode. In slave mode, SCLKN1 operates asynchronously from all other CS493XX clocks. In

master mode, SCLKN1 is derived from the CS493XX internal clock generator. In either master

or slave mode, the active edge of SCLKN1 can be programmed by the DSP. For applications

supporting PES layer synchronization this pin can be used as STCCLK2, which provides a path

to the internal STC 33 bit counter. BIDIRECTIONAL - Default: INPUT

LRCLKN1—PCM Audio Input Sample Rate Clock: Pin 26

Bidirectional digital-audio frame clock that is an output in master mode and an input in slave

mode. LRCLKN1 typically is run at the sampling frequency. In slave mode, LRCLKN1

operates asynchronously from all other CS493XX clocks. In master mode, LRCLKN1 is

derived from the CS493XX internal clock generator. In either master or slave mode, the

polarity of LRCLKN1 for a particular subframe can be programmed by the DSP.

BIDIRECTIONAL - Default: INPUT

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