CS49310 datasheet(7/86 Pages) CIRRUS

7 / 86 page

CS49300 Family DSP

DS339PP4

1.5. Switching Characteristics — RESET

(TA = 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Notes: 1. The minimum RESET pulse listed above is valid only when using the recommended pull-up/pull-down

resistors on the RD, WR, PSEL and ABOOT mode pins. For Rev. D and older parts, pull-up/pull-down

resistors may be 4.7 k or 3.3 k. For Rev. E and newer parts, pull-up/pull-down resistors must be 3.3 k.

2. This specification is characterized but not production tested.

1.6. Switching Characteristics — CLKIN

(TA = 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)

Parameter

Symbol

Min

Max

Unit

RESET minimum pulse width low (-CL)

(Note 1)

Trstl

100

µs

RESET minimum pulse width low (-IL)

(Note 1)

Trstl

530

µs

All bidirectional pins high-Z after RESET low

(Note 2)

Trst2z

-50

Configuration bits setup before RESET high

Trstsu

Configuration bits hold after RESET high

Trsthld

Parameter

Symbol

Min

Max

Unit

CLKIN period for internal DSP clock mode

Tclki

3800

CLKIN high time for internal DSP clock mode

Tclkih

CLKIN low time for internal DSP clock mode

Tclkil

R ESET

rs t2 z

rs tl

rs ts u

rs th ld

RD, W R ,

PSEL, ABO O T

A ll B idirectional

Pins

Figure 1. RESET Timing

CL KIN

Tclkih

Tclkil

Tclki

Figure 2. CLKIN with CLKSEL = VSS = PLL Enable

CS49310 数据表(PDF) 7 Page - Cirrus Logic

CS49310 数据表(HTML) 7 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

数据表下载