CS49310 datasheet(71/86 Pages) CIRRUS

71 / 86 page

CS49300 Family DSP

DS339PP4

configured to provide a 128Fs, 256Fs or 512Fs

clock, where Fs is the output sample rate.

SCLK is the bit clock used to clock data out on

AUDATA0,

AUDATA1,

AUDATA2

and

AUDATA3. LRCLK is the data framing clock

whose frequency is typically equal to the sampling

frequency. Both LRCLK and SCLK can be

configured as either inputs (Slave mode) or outputs

(Master mode). When LRCLK and SCLK are

configured as inputs, MCLK is a don’t care as an

input. When LRCLK and SCLK are configured as

outputs, they are derived from MCLK. Whether

MCLK is configured as an input or an output, an

internal divider from the MCLK signal is used to

produce LRCLK and SCLK. The ratios shown in

Table 16 give the possible SCLK values for

different MCLK frequencies (all values in terms of

the sampling frequency, Fs).

AUDAT0 is configurable to provide six, four, or

two

channels.

AUDATA1,

AUDATA2

and

AUDATA3 can both output two channels of data.

Typically

the

AUDATA0,

AUDATA1,

AUDATA2 and AUDATA3 outputs are used in

left justified, I2S or right justified modes.

AUDATA0, AUDATA1 and AUDATA2 are used

for 5.1 output, presenting all six channels of

surround

sound

(Left,

Center,

Right,

Left

Surround, Right Surround and Subwoofer).

AUDATA3

can

used

with

AUDATA0,

AUDATA1 and AUDATA2 to support 7.1 output.

Alternatively AUDATA3 can be used for dual zone

support. AUDATA3 is multiplexed with the

XMT958 output so only one can be used at any one

time.

Table 17 shows the mapping of DAO channels to

actual outputs when not in a multichannel mode.

Please consult the application code user’s guides to

determine what modes are supported by the

application code being used.

10.5.1.IEC60958 Output

The XMT958 output is shared with the AUDATA3

output so only one can be used at any one time. The

XMT958 output provides a CMOS level bi phase

encoded output. The XMT958 function can be

internally clocked from the PLL or from an MCLK

input if MCLK is 256Fs or 512Fs. All channel

status information can be used when using software

which supports this functionality. This output can

be used for either 2 channel PCM output or

compressed data output in accordance with

IEC61937. To be fully IEC60958 compliant this

output would need to be buffered through an

RS422 device or an optocoupler as its outputs are

only CMOS. Please consult software user’s guide

to determine if this pin is supported by the

download code being used.

MCLK

(Fs)

SCLK (Fs)

128

256

512

128

384**

256

XXX

512

XXXX

** For MCLK as an input only

Table 16. MCLK/SCLK Master Mode Ratios

DAO_Channel

Subframe

Signal

Left

AUDATA0

Right

AUDATA0

Left

AUDATA1

Right

AUDATA1

Left

AUDATA2

Right

AUDATA2

Left

AUDATA3

Right

AUDATA3

Table 17. Output Channel Mapping

CS49310 数据表(PDF) 71 Page - Cirrus Logic

CS49310 数据表(HTML) 71 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

数据表下载

链接网址

CS49310 数据表(PDF) 71 Page - Cirrus Logic

CS49310 数据表(HTML) 71 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

数据表 下载

链接网址

数据表下载