数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

CS49310 数据表(PDF) 16 Page - Cirrus Logic

部件名 CS49310
功能描述  Multi-Standard Audio Decoder Family
PDF  86 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS49310 数据表(HTML) 16 Page - Cirrus Logic

Back Button CS49310 Datasheet HTML 12Page - Cirrus Logic CS49310 Datasheet HTML 13Page - Cirrus Logic CS49310 Datasheet HTML 14Page - Cirrus Logic CS49310 Datasheet HTML 15Page - Cirrus Logic CS49310 Datasheet HTML 16Page - Cirrus Logic CS49310 Datasheet HTML 17Page - Cirrus Logic CS49310 Datasheet HTML 18Page - Cirrus Logic CS49310 Datasheet HTML 19Page - Cirrus Logic CS49310 Datasheet HTML 20Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 16 / 86 page
background image
CS49300 Family DSP
16
DS339PP4
1.11. Switching Characteristics — Digital Audio Input
(TA = 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)
Notes: 1. Master mode timing specifications are characterized, not production tested.
2. Master mode is defined as the CS493XX driving LRCLKN1(2) and SCLKN1(2). Master or Slave mode
can be programmed.
3. This timing parameter is defined from the non-active edge of SCLKN1(2). The active edge of
SCLKN1(2) is the point at which the data is valid.
4. This timing parameter is defined from the active edge of SCLKN1(2). The active edge of SCLKN1(2) is
the point at which the data is valid.
5. Slave mode is defined as SCLKN1(2) and LRCLKN1(2) being driven by an external source.
Parameter
Symbol
Min
Max
Unit
SCLKN1(2) period for both Master and Slave mode
(Note 1)
Tsclki
40
-
ns
SCLKN1(2) duty cycle for Master and Slave mode
(Note 1)
45
55
%
Master Mode
(Note 1, 2)
LRCLKN1(2) delay after SCLKN1(2) transition
(Note 3)
Tlrds
-10
ns
SDATAN1(2) setup to SCLKN1(2) transition
(Note 4)
Tsdsum
10
-
ns
SDATAN1(2) hold time after SCLKN1(2) transition
(Note 4)
Tsdhm
5-
ns
Slave Mode
(Note 5)
Time from active edge of SCLKN1(2) to LRCLKN1(2) transition
Tstlr
10
-
ns
Time from LRCLKN1(2) transition to SCLKN1(2) active edge
Tlrts
10
-
ns
SDATAN1(2) setup to SCLKN1(2) transition
(Note 4)
Tsdsus
5-
ns
SDATAN1(2) hold time after SCLKN1(2) transition
(Note 4)
Tsdhs
5-
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com