CS49310 datasheet(35/86 Pages) CIRRUS

35 / 86 page

CS49300 Family DSP

DS339PP4

transaction.

Understanding the role of INTREQ is important for

successful communication. INTREQ is guaranteed

to remain low (once it has gone low) until the

second to last rising edge of SCCLK of the last byte

to be transferred out of the CS493XX. If there is no

more data to be transferred, INTREQ will go high

at this point. For SPI this is the rising edge for the

second to last bit of the last byte to be transferred.

After going high, INTREQ is guaranteed to stay

high until the next rising edge of SCCLK. This end

of transfer condition signals the host to end the read

transaction by clocking the last data bit out and

raising CS. If INTREQ is still low after the second

to last rising edge of SCCLK, the host should

continue reading data from the serial control port.

It should be noted that all data should be read out of

the serial control port during one cycle or a loss of

data will occur. In other words, all data should be

read out of the chip until INTREQ signals the last

byte by going high as described above. Please see

Section 6.1.3, “INTREQ Behavior: A Special

Case” on page 39 for a more detailed description of

INTREQ behavior.

Figure 21, "SPI Timing" on page 36 timing

diagram shows the relative edges of the control

lines for an SPI read and write.

6.1.2. I2C Communication

I2C

communication

with

the

CS493XX

accomplished with 3 communication lines: serial

control

clock,

bi-directional

serial

data

input/output line and an interrupt request line to

signal that the DSP has data to transmit to the host.

See Figure 4, "I2C® Communication Signals" on

page 35 shows the mnemonic, pin name, and pin

number of each of these signals on the CS493XX.

Typically in I2C® communication SCDIO is an

open drain line with a pull-up. A logic one is placed

on the line by three-stating the output and allowing

the pull-up to raise the line. At this point another

device can drive the line low if necessary. Three-

stating SCDIO can have two effects: 1. To send out

a one when writing data or sending a “no

acknowledge”; 2. release the line when another

chip is writing data.

6.1.2.1.Writing in I2C®

When writing to the device in I2C® the same

protocol will be used whether writing a byte, a

message or even an application code image. The

examples shown in this document can be expanded

to fit any write situation. Figure 23 shows a typical

write sequence:

The following is a detailed description of an I2C®

write sequence with the CS493XX.

1) An I2C® transfer is initiated with an I2C® start

condition which is defined as the data (SCDIO)

line falling while the clock (SCCLK) is held

high.

2) Next a 7-bit address with the read/write bit set

low for a write should be sent to the CS493XX.

The address for the CS493XX defaults to

0000000b. It is necessary to clock this address

in prior to any transfer in order for the

CS493XX to accept the write. In other words a

byte of 0x00 should be clocked into the device

preceding any write. The 0x00 byte represents

the 7 bit of address (0000000b) and the

read/write bit set to 0 to designate a write.

Mnemonic

Pin Name

Pin Number

Serial Clock

SCCLK

Bi-Directional Data

SCDIO

Interrupt Request

INTREQ

Table 4. I2C® Communication Signals

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