CS49310 datasheet(84/86 Pages) CIRRUS

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CS49300 Family DSP

DS339PP4

SDATAN1—PCM Audio Data Input Number One: Pin 22

Digital-audio data input that can accept from one to six channels of compressed or PCM data.

SDATAN1 can be sampled with either edge of SCLKN1, depending on how SCLKN1 has been

configured. INPUT

CMPCLK, SCLKN2—PCM Audio Input Bit Clock: Pin 28

Bidirectional digital-audio bit clock that is an output in master mode and an input in slave

mode. In slave mode, SCLKN2 operates asynchronously from all other CS493XX clocks. In

master mode, SCLKN2 is derived from the CS493XX internal clock generator. In either master

or slave mode, the active edge of SCLKN2 can be programmed by the DSP. If the CDI is

configured for bursty delivery, CMPCLK is an input used to sample CMPDAT.

BIDIRECTIONAL - Default: INPUT

CMPREQ, LRCLKN2—PCM Audio Input Sample Rate Clock: Pin 29

When the CDI is configured as a digital audio input, this pin serves as a bidirectional digital-

audio frame clock that is an output in master mode and an input in slave mode. LRCLKN2

typically is run at the sampling frequency. In slave mode, LRCLKN2 operates asynchronously

from all other CS493XX clocks. In master mode, LRCLKN2 is derived from the CS493XX

internal clock generator. In either master or slave mode, the polarity of LRCLKN2 for a

particular subframe can be programmed by the DSP. When the CDI is configured for bursty

delivery, or parallel audio data delivery is being used, CMPREQ is an output which serves as

an internal FIFO monitor. CMPREQ is an active low signal that indicates when another block

of data can be accepted. BIDIRECTIONAL - Default: INPUT

CMPDAT, SDATAN2—PCM Audio Data Input Number Two: Pin 27

Digital-audio data input that can accept from one to six channels of compressed or PCM data.

SDATAN2 can be sampled with either edge of SCLKN2, depending on how SCLKN2 has been

configured. Similarly CMPDAT is the compressed data input pin when the CDI is configured

for bursty delivery. When in this mode, the CS493XX internal PLL is driven by the clock

recovered from the incoming data stream. INPUT

DC—Reserved: Pin 38

This pin is reserved and should be pulled up with an external 4.7k resistor.

DD—Reserved: Pin 37

This pin is reserved and should be pulled up with an external 4.7k resistor.

CS49310 数据表(PDF) 84 Page - Cirrus Logic