RM0319 datasheet(219/368 Pages) STMICROELECTRONICS

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RM0319

Asynchronous serial ports (UART)

Doc ID 022640 Rev 3

219/368

16.3

Functional description

This chapter describes the main interfaces of the UART block.

Figure 79 shows the UART block diagram.

Figure 79.

UART block diagram

Note:

Applicable for UART0 - UART1 (only for two modes)

16.3.1

APB Interface

The APB Interface block generates read and write decodes for accesses to control and

status registers (CSRs) as well as to transmit/receive FIFO memories.

16.3.2

The Register Block allows to store data written, or to be read across the APB Interface.

nUARTRST

PCLK

PRESETn

PSEL

PENABLE

PWRITE

PADDR[11:2]

PWDATA[15:0]

PRDATA[15:0]

UARTCLK

APB interface

and register

block

UARTRXDMACLR

UARTTXDMACLR

UARTRXDMASREQ

UARTRXDMABREQ

UARTTXDMASREQ

UARTTXDMABREQ

DMA

Interface

FIFO status

and interrupt

generation

UARTTXINTR

UARTRXINTR

UARTMSINTR

UARTRTINTR

UARTEINTR

UARTINTR

nUARTCTS

nUARTRI

nUARTDSR

nUARTDCD

nUARTDTR

nUARTRTS

nUARTOUT1

nUARTOUT2

16x12

Receive

FIFO

Transmitter

Receiver

UARTTXD

UARTRXD

16x8

Transmit

FIFO

Baud rate

generator

FIFO

flags

Transmit

FIFO

status

Receiv

FIFO

status

Baud rate divisor

Control and status

Baud16

txd[7:0]

rxd[11:0]

Read data[11:0]

Write data[7:0]

Note 1

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