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PM0223 数据表(PDF) 68 Page - STMicroelectronics |
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PM0223 数据表(HTML) 68 Page - STMicroelectronics |
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68 / 110 page ![]() The STM32L0 Cortex-M0+ Instruction Set PM0223 68/110 DocID025763 Rev 1 3.7 Miscellaneous instructions Table 24 shows the remaining STM32L0 Cortex-M0+ instructions : Table 24. Miscellaneous instructions Mnemonic Brief description See BKPT Breakpoint 3.7.1: BKPT on page 69. CPSID Change Processor State, Disable Interrupts 3.7.2: CPS on page 70. CPSIE Change Processor State, Enable Interrupts 3.7.2: CPS on page 70. DMB Data Memory Barrier 3.7.3: DMB on page 71. DSB Data Synchronization Barrier 3.7.4: DSB on page 72. ISB Instruction Synchronization Barrier 3.7.5: ISB on page 73. MRS Move from special register to register 3.7.6: MRS on page 74. MSR Move from register to special register 3.7.7: MSR on page 75. NOP No Operation 3.7.7: MSR on page 75. SEV Send Event 3.7.9: SEV on page 77. SVC Supervisor Call 3.7.10: SVC on page 78. WFE Wait For Event 3.7.11: WFE on page 79. WFI Wait For Interrupt 3.7.12: WFI on page 80. |
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