PM0223 datasheet(86/110 Pages) STMICROELECTRONICS

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STM32L0 Core Peripherals

PM0223

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Find the NVIC_IPR number and byte offset for interrupt M as follows:

•

The corresponding NVIC_IPR number, N, is given by N = N DIV 4.

•

The byte offset of the required Priority field in this register is M MOD 4, where:

–

Byte offset 0 refers to register bits[7:0].

–

Byte offset 1 refers to register bits[15:8].

–

Byte offset 2 refers to register bits[23:16].

–

Byte offset 3 refers to register bits[31:24].

4.2.7

Level-sensitive and pulse interrupts

STM32L0 interrupts are both level-sensitive and pulse-sensitive. Pulse interrupts are also

described as edge-triggered interrupts.

A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal.

Typically this happens because the ISR accesses the peripheral, causing it to clear the

interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the

rising edge of the processor clock. To ensure the NVIC detects the interrupt, the peripheral

must assert the interrupt signal for at least one clock cycle, during which the NVIC detects

the pulse and latches the interrupt.

When the processor enters the ISR, it automatically removes the pending state from the

interrupt, see Hardware and software control of interrupts on page 86. For a level-sensitive

interrupt, if the signal is not deasserted before the processor returns from the ISR, the

interrupt becomes pending again, and the processor must execute its ISR again. This

means that the peripheral can hold the interrupt signal asserted until it no longer requires

servicing.

Hardware and software control of interrupts

The STM32L0 Cortex-M0+ latches all interrupts. A peripheral interrupt becomes pending for

one of the following reasons:

•

The NVIC detects that the interrupt signal is active and the corresponding interrupt is

not active.

•

The NVIC detects a rising edge on the interrupt signal.

•

Software writes to the corresponding interrupt set-pending register bit, see 4.2.4:

Interrupt Set-pending Register on page 84.

A pending interrupt remains pending until one of the following:

•

The processor enters the ISR for the interrupt. This changes the state of the interrupt

from pending to active. Then:

–

For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC

samples the interrupt signal. If the signal is asserted, the state of the interrupt

changes to pending, which might cause the processor to immediately re-enter the

ISR. Otherwise, the state of the interrupt changes to inactive.

–

For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this

is pulsed the state of the interrupt changes to pending and active. In this case,

when the processor returns from the ISR the state of the interrupt changes to

pending, which might cause the processor to immediately re-enter the ISR. If the

interrupt signal is not pulsed while the processor is in the ISR, when the processor

returns from the ISR the state of the interrupt changes to inactive.

•

Software writes to the corresponding interrupt clear-pending register bit.

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