PM0223 datasheet(33/110 Pages) STMICROELECTRONICS

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PM0223

The STM32L0 Cortex-M0+ Processor

2.4

Fault handling

Faults are a subset of exceptions, see 2.3: Exception model on page 26. All faults result in

the HardFault exception being taken or cause Lockup if they occur in the NMI or HardFault

handler. The faults are:

•

Execution of an SVC instruction at a priority equal or higher than SVCall.

•

Execution of a BKPT instruction without a debugger attached.

•

A system-generated bus error on a load or store.

•

Execution of an instruction from an XN memory address.

•

Execution of an instruction from a location for which the system generates a bus fault.

•

A system-generated bus error on a vector fetch.

•

Execution of an Undefined instruction.

•

Execution of an instruction when not in Thumb state as a result of the T-bit being

previously cleared to 0.

•

An attempted load or store to an unaligned address.

•

An MPU fault because of a privilege violation or an attempt to access an unmanaged

region.

Note:

Only Reset and NMI can preempt the fixed priority HardFault handler. A HardFault can

preempt any exception other than Reset, NMI, or another HardFault.

2.4.1

Lockup

The processor enters a Lockup state if a fault occurs when executing the NMI or HardFault

handlers, or if the system generates a bus error when unstacking the PSR on an exception

return using the MSP. When the processor is in Lockup state it does not execute any

instructions. The processor remains in Lockup state until one of the following occurs:

•

It is reset.

•

A debugger halts it.

•

An NMI occurs and the current Lockup is in the HardFault handler.

Note:

If Lockup state occurs in the NMI handler a subsequent NMI does not cause the processor

to leave Lockup state.

2.5

Power management

The STM32L0 Cortex-M0+ processor sleep modes reduce power consumption:

•

A sleep mode, that stops the processor clock.

•

A deep sleep mode, that enters ultra low-power modes.

The SLEEPDEEP bit of the SCR selects which sleep mode is used, see 4.3.6: System Con-

trol Register on page 92. When entering the deep sleep mode, the PDSS bit in PWR_CR

power modes" for details.

This section describes the mechanisms for entering sleep mode, and the conditions for wak-

ing up from sleep mode.

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