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PM0223 数据表(PDF) 20 Page - STMicroelectronics |
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PM0223 数据表(HTML) 20 Page - STMicroelectronics |
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20 / 110 page  The STM32L0 Cortex-M0+ Processor PM0223 20/110 DocID025763 Rev 1 2.2 Memory model This section describes the processor memory map and the behavior of memory accesses. The processor has a fixed memory map that provides up to 4GB of addressable memory. The memory map is: Figure 5. Memory map The processor reserves regions of the Private Peripheral Bus (PPB) address range for core peripheral registers, see 1.3: About the STM32L0 Cortex-M0+ processor and core peripher- als on page 9. 2.2.1 Memory regions, types and attributes The memory map and the programming of the MPU splits into regions. Each region has a defined memory type, and some regions have additional memory attributes. The memory type and attributes determine the behavior of accesses to the region. |
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