PM0223 datasheet(30/110 Pages) STMICROELECTRONICS

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The STM32L0 Cortex-M0+ Processor

PM0223

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2.3.5

Exception priorities

As Table 13 on page 27 shows, all exceptions have an associated priority, with:

•

A lower priority value indicating a higher priority.

•

Configurable priorities for all exceptions except Reset, HardFault, and NMI.

If software does not configure any priorities, then all exceptions with a configurable priority

have a priority of 0. For information about configuring exception priorities see

•

4.3.8: System Handler Priority Registers on page 94

•

I4.2.6: Interrupt Priority Registers on page 85.

Note:

Configurable priority values are in the range 0-192, in steps of 64. The Reset, HardFault,

and NMI exceptions, with fixed negative priority values, always have higher priority than any

other exception.

Assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that

IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is pro-

cessed before IRQ[0].

If multiple pending exceptions have the same priority, the pending exception with the lowest

exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending

and have the same priority, then IRQ[0] is processed before IRQ[1].

When the processor is executing an exception handler, the exception handler is preempted

if a higher priority exception occurs. If an exception occurs with the same priority as the

exception being handled, the handler is not preempted, irrespective of the exception num-

ber. However, the status of the new interrupt changes to pending.

2.3.6

Exception entry and return

Descriptions of exception handling use the following terms:

Preemption When the processor is executing an exception handler, an exception can

preempt the exception handler if its priority is higher than the priority of the

exception being handled.

When one exception preempts another, the exceptions are called nested

exceptions. See Exception entry on page 31 for more information.

Return

This occurs when the exception handler is completed, and:

•

There is no pending exception with sufficient priority to be serviced.

•

The completed exception handler was not handling a late-arriving

exception.

The processor pops the stack and restores the processor state to the state it

had before the interrupt occurred. See Exception return on page 32 for more

information.

Tail-chaining This mechanism speeds up exception servicing. On completion of an

exception handler, if there is a pending exception that meets the

requirements for exception entry, the stack pop is skipped and control

transfers to the new exception handler.

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