PM0223 datasheet(47/110 Pages) STMICROELECTRONICS

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PM0223

The STM32L0 Cortex-M0+ Instruction Set

3.4.2

LDR and STR, immediate offset

Load and Store with immediate offset.

Syntax

LDR Rt, [<Rn | SP> {, #imm}]

LDR<B|H> Rt, [Rn {, #imm}]

STR Rt, [<Rn | SP>, {,#imm}]

STR<B|H> Rt, [Rn {,#imm}]

where:

Operation

LDR

, LDRB and LDRH instructions load the register specified by Rt with either a word, byte

or halfword data value from memory. Sizes less than word are zero extended to 32-bits

before being written to the register specified by Rt.

STR, STRB

and STRH instructions store the word, least-significant byte or lower halfword

contained in the single register specified by Rt in to memory. The memory address to load

from or store to is the sum of the value in the register specified by either Rn or SP and the

immediate value imm.

Restrictions

In these instructions:

•

and Rn must only specify R0-R7.

•

imm

must be between:

–

0 and 1020 and an integer multiple of four for LDR and STR using SP as the base

–

0 and 124 and an integer multiple of four for LDR and STR using R0-R7 as the

base register.

–

0 and 62 and an integer multiple of two for LDRH and STRH.

–

0 and 31 for LDRB and STRB.

•

The computed address must be divisible by the number of bytes in the transaction, see

3.3.4: Address alignment on page 42.

Condition flags

These instructions do not change the flags.

Examples

LDR R4, [R7 ; Loads R4 from the address in R7.

STR R2,[R0,#const-struc] ; const-struc is an expression evaluating

; to a constant in the range 0-1020.

Is the register to load or store.

Is the register on which the memory address is based

imm

Is an offset from Rn. If imm is omitted, it is assumed to be zero.

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