PM0223 datasheet(37/110 Pages) STMICROELECTRONICS

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PM0223

The STM32L0 Cortex-M0+ Instruction Set

ISB

Instruction

Synchronization

Barrier

3.7.5 on page 73.

LDM

Rn{!}, reglist

Load Multiple

registers, increment

after

3.4.5 on page 50.

LDR

Rt, label

Load Register from

PC-relative address

3.4.2 on page 47.

LDR

Rt, [Rn, <Rm|#imm>]

Load Register with

word

3.4.2 on page 47.

LDRB

Rt, [Rn, <Rm|#imm>]

Load Register with

byte

3.4.2 on page 47.

LDRH

Rt, [Rn, <Rm|#imm>]

Load Register with

halfword

3.4.2 on page 47.

LDRSB

Rt, [Rn, <Rm|#imm>]

Load Register with

signed byte

3.4.2 on page 47.

LDRSH

Rt, [Rn, <Rm|#imm>]

Load Register with

signed halfword

3.4.2 on page 47.

LSLS

{Rd,} Rn, <Rs|#imm>

Logical Shift Left

N,Z,C

3.5.3 on page 57.

LSRS

{Rd,} Rn, <Rs|#imm>

Logical Shift Right

N,Z,C

3.5.3 on page 57.

MOV{S

}

Rd, Rm

Move

N,Z

3.5.5 on page 60.

MRS

Rd, spec_reg

Move to general

3.7.6 on page 74.

MSR

spec_reg, Rm

Move to special

N,Z,C,V

3.7.7 on page 75.

MULS

Rd, Rn, Rm

Multiply, 32-bit result

N,Z

3.5.6 on page 61.

MVNS

Rd, Rm

Bitwise NOT

N,Z

3.5.5 on page 60.

NOP

No Operation

3.7.8 on page 76.

ORRS

{Rd,} Rn, Rm

Logical OR

N,Z

3.5.2 on page 56.

POP

reglist

Pop registers from

stack

3.4.6 on page 52.

PUSH

reglist

Push registers onto

stack

3.4.6 on page 52.

REV

Rd, Rm

Byte-Reverse word

3.5.7 on page 62.

REV16

Rd, Rm

Byte-Reverse packed

halfwords

3.5.7 on page 62.

REVSH

Rd, Rm

Byte-Reverse signed

halfword

3.5.7 on page 62.

RORS

{Rd,} Rn, Rs

Rotate Right

N,Z,C

3.5.3 on page 57.

Table 15. STM32L0 Cortex-M0+ instructions (continued)

Mnemonic

Operands

Brief description

Flags

Section

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