PM0223 datasheet(14/110 Pages) STMICROELECTRONICS

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The STM32L0 Cortex-M0+ Processor

PM0223

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DocID025763 Rev 1

General-purpose registers

R0-R12 are 32-bit general-purpose registers for data operations.

Stack Pointer

The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register

indicates the stack pointer to use:

•

0 = Main Stack Pointer (MSP). This is the reset value.

•

1 = Process Stack Pointer (PSP).

On reset, the processor loads the MSP with the value from address 0x00000000.

Link Register

The Link Register (LR) is register R14. It stores the return information for subroutines, func-

tion calls, and exceptions. On reset, the LR value is Unknown.

Program Counter

The Program Counter (PC) is register R15. It contains the current program address. On

reset, the processor loads the PC with the value of the reset vector, which is at address

0x00000004

. Bit[0] of the value is loaded into the EPSR T-bit at reset and must be 1.

Program Status Register

The Program Status Register (PSR) combines:

•

Application Program Status Register (APSR).

•

Interrupt Program Status Register (IPSR).

•

Execution Program Status Register (EPSR).

These registers are allocated as mutually exclusive bitfields within the 32-bit PSR. The PSR

bit assignments are:

APSR

Unknown

Application Program Status Register on page 15

IPSR

0x00000000

Interrupt Program Status Register on page 16

EPSR

Unknown

Execution Program Status Register on page 16

PRIMASK

0x00000000

Priority Mask Register on page 17

CONTROL

0x00000000

CONTROL register on page 17

1. Describes access type during program execution in Thread mode and Handler mode. Debug access can

differ.

2. Bit[24] is the T-bit and is loaded from bit[0] of the reset vector.

Table 3. Core register set summary (continued)

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