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PM0223 数据表(PDF) 89 Page - STMicroelectronics |
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PM0223 数据表(HTML) 89 Page - STMicroelectronics |
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89 / 110 page  DocID025763 Rev 1 89/110 PM0223 STM32L0 Core Peripherals 108 4.3.3 Interrupt Control and State Register (ICSR) The ICSR: • Provides: – A set-pending bit for the Non-Maskable Interrupt (NMI) exception. – Set-pending and clear-pending bits for the PendSV and SysTick exceptions. • Indicates: – The exception number of the highest priority pending exception. See the register summary in Table 30 on page 88 for the ICSR attributes. The bit assignments are Bits 31:24 Implementer: Implementer code 0x41 : ARM Bits 23:20 Variant: Major revision number n in the rnpm revision status: 0x0 : Revision 0 Bits 19:16 Architecture: Constant that defines the architecture of the processor: 0xC : ARMv6-M architecture Bits 15:4 PartNo: Part number of the processor 0xC60 : = STM32L0 Cortex-M0+ Bits 3:0 Revision: Minor revision number m in the rnpm revision status: 0x1 : patch 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NMIPE NDSET Reserved PEND SVSET PEND SVCLR PEND STSET PENDS TCLR Reserved ISRPE NDING Reserved VECTPENDING[6:4] rw rw w rw w r r r r 15 14 13 12 11 10 9 8 76 5432 1 0 VECTPENDING[3:0] RETOB ASE Reserved VECTACTIVE[8:0] r rrrr rw rw rw rw rw rw rw rw rw |
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