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数据搜索系统，热门电子元器件搜索 |
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PM0223 数据表(PDF) 92 Page - STMicroelectronics |
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PM0223 数据表(HTML) 92 Page - STMicroelectronics |
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92 / 110 page  STM32L0 Core Peripherals PM0223 92/110 DocID025763 Rev 1 4.3.6 System Control Register The SCR controls features of entry to and exit from low power state. See the register summary in Table 30 on page 88 for its attributes. The bit assignments are 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VECTKEYSTAT rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 76 5432 1 0 ENDIA NESS Reserved SYS RESET REQ VECT CLR ACTIVE Reserv ed r ww Bits 31:16 VECTKEY Register key Register key: Reads as Unknown On writes, write 0x05FA to VECTKEY, otherwise the write is ignored. Bit 15 ENDIANESS Data endianness bit Reads as 0. 0: Little-endian Bits 14:3 Reserved Bit 2 SYSRESETREQ System reset request: 0: No effect 1: Requests a system level reset. This bit reads as 0. Bit 1 VECTCLRACTIVE Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is unpredictable. Bit 0 Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 76 5432 1 0 Reserved SEVON PEND Res. SLEEP DEEP SLEEP ON EXIT Res. rw rw rw |
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