PM0223 datasheet(18/110 Pages) STMICROELECTRONICS

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The STM32L0 Cortex-M0+ Processor

PM0223

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Figure 4. Control bit assignment

Handler mode always uses the MSP, so the processor ignores explicit writes to the active

stack pointer bit of the CONTROL register when in Handler mode. The exception entry and

return mechanisms automatically update the CONTROL register.

In an OS environment, it is recommended that threads running in Thread mode use the pro-

cess stack and the kernel and exception handlers use the main stack.

By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode to

the PSP, use the MSR instruction to set the active stack pointer bit to 1, 3.7.6: MRS on

page 74

Note:

When changing the stack pointer, software must use an ISB instruction immediately after the

MSR

instruction. This ensures that instructions after the ISB execute using the new stack

pointer. See 3.7.5: ISB on page 73.

2.1.4

Exceptions and interrupts

The STM32L0 Cortex-M0+ processor supports interrupts and system exceptions. The pro-

cessor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all excep-

tions. An interrupt or exception changes the normal flow of software control. The processor

uses Handler mode to handle all exceptions except for reset. See Exception entry on

page 31 and Exception return on page 32 for more information.

The NVIC registers control interrupt handling. See 4.2: Nested Vectored Interrupt Controller

on page 82 for more information.

Table 9. Control register bit assignments

Bits

Name

Function

[31:2]

Reserved.

[1]

SPSEL

Defines the current stack:

0 = MSP is the current stack pointer.

1 = PSP is the current stack pointer.

In Handler mode this bit reads as zero and ignores writes.

[0]

nPRIV

Defines the Thread mode privilege level:

0 = Privileged.

1 = Unprivileged.

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