数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

PM0223 数据表(PDF) 94 Page - STMicroelectronics

部件名 PM0223
功能描述  This programming manual provides information for application and system-level software developers
PDF  110 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

PM0223 数据表(HTML) 94 Page - STMicroelectronics

Back Button PM0223 Datasheet HTML 90Page - STMicroelectronics PM0223 Datasheet HTML 91Page - STMicroelectronics PM0223 Datasheet HTML 92Page - STMicroelectronics PM0223 Datasheet HTML 93Page - STMicroelectronics PM0223 Datasheet HTML 94Page - STMicroelectronics PM0223 Datasheet HTML 95Page - STMicroelectronics PM0223 Datasheet HTML 96Page - STMicroelectronics PM0223 Datasheet HTML 97Page - STMicroelectronics PM0223 Datasheet HTML 98Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 94 / 110 page
background image
STM32L0 Core Peripherals
PM0223
94/110
DocID025763 Rev 1
4.3.8
System Handler Priority Registers
The SHPR2-SHPR3 registers set the priority level, 0 to 192, of the system exception
handlers that have configurable priority.
SHPR2-SHPR3 are word accessible. See the register summary in for their attributes.
To access the system exception priority level using CMSIS, use the following CMSIS
functions:
uint32_t NVIC_GetPriority(IRQn_Type IRQn)
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
The input parameter IRQn is the IRQ number, see Table 13 on page 27 for more
information.
The system handlers, and the priority field and register for each handler are:
Each PRI_N field is 8 bits wide, but the processor implements only bits[7:6] of each field,
and bits[5:0] read as zero and ignore writes.
System Handler Priority Register 2
The bit assignments are:
Bits 8:4
Reserved, must be kept cleared
Bit 3
UNALIGN_ TRP
Always reads as one, indicates that all unaligned accesses generate a HardFault.
Bit 2:0
Reserved, must be kept cleared
Table 32. System fault handler priority fields
Handler
Field
Register description
SVCall
PRI_11
System Handler Priority Register 2 on page 94.
PendSV
PRI_14
System Handler Priority Register 3 on page 95.
SysTick
PRI_15
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
PRI_6[7:4]
PRI_6[3:0]
rw
rw
rw
rw
r
r
r
r
15
14
13
12
11
10
9
8
76
5432
1
0
PRI_5[7:4]
PRI_5[3:0]
PRI_4[7:4]
PRI_4[7:4]
rw
rw
rw
rw
r
r
r
r
rw
rw
rw
rw
r
r
r
r
Bits 31:24
PRI_11: Priority of system handler 11, SVCall.
Bits 23:0
Reserved, must be kept cleared



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com