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PM0223 数据表(PDF) 96 Page - STMicroelectronics |
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PM0223 数据表(HTML) 96 Page - STMicroelectronics |
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96 / 110 page  STM32L0 Core Peripherals PM0223 96/110 DocID025763 Rev 1 4.4.1 SysTick Control and Status Register (STK_CSR) The SYST_CSR enables the SysTick features. See the register summary in Table 33 on page 95 for its attributes. The bit assignments are: 4.4.2 SysTick Reload Value Register (STK_RVR) The STK_RVR specifies the start value to load into the SYST_CVR. See the register summary in Table 33 on page 95 for its attributes. The bit assignments are: Calculating the RELOAD value The RELOAD value can be any value in the range 0x00000001-0x00FFFFFF. You can program a value of 0, but this has no effect because the SysTick exception request and COUNTFLAG are activated when counting from 1 to 0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved rc_r 15 14 13 12 11 10 9 8 76 5432 1 0 Reserved rw rw rw Bits31:17 Reserved, must be kept cleared. Bit 16 COUNTFLAG Returns 1 if timer counted to 0 since the last read of this register. Bits 15:3 Reserved, must be kept cleared. Bit 2 CLKSOURCE Selects the SysTick timer clock source: 0 = External reference clock. 1 = Processor clock. Bit 1 TICKINT Enables SysTick exception request: 0 = Counting down to zero does not assert the SysTick exception request. 1 = Counting down to zero to asserts the SysTick exception request. Bit 0 ENABLE Enables the counter: 0 = Counter disabled. 1 = Counter enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved RELOAD rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RELOAD rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits31:24 Reserved, must be kept cleared. Bits 23:0 RELOAD Value to load into the STK_CVR when the counter is enabled and when it reaches 0, see Calculating the RELOAD value on page 96. |
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