PM0223 datasheet(17/110 Pages) STMICROELECTRONICS

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PM0223

The STM32L0 Cortex-M0+ Processor

Attempts by application software to read the EPSR directly using the MRS instruction always

return zero. Attempts to write the EPSR using the MRS instruction are ignored. Fault han-

dlers can examine the EPSR value in the stacked PSR to determine the cause of the fault.

See Exception entry and return on page 30. The following can clear the T bit to 0:

•

Instructions BLX, BX and POP{PC}.

•

Restoration from the stacked xPSR value on an exception return.

•

Bit[0] of the vector value on an exception entry.

Attempting to execute instructions when the T bit is 0 results in a HardFault or Lockup. See

2.4.1: Lockup on page 33 for more information.

Interruptible-restartable instructions

The interruptible-restartable instructions are LDM and STM, PUSH, POP, and MULS. When

an interrupt occurs during the execution of one of these instructions, the processor

abandons execution of the instruction. After servicing the interrupt, the processor restarts

execution of the instruction from the beginning.

Exception mask register

The exception mask register disables the handling of exceptions by the processor. Disable

exceptions where they might impact on timing critical tasks or code sequences requiring

atomicity.

To disable or re-enable exceptions, use the MSR and MRS instructions, or the CPS instruc-

tion, to change the value of PRIMASK. 3.7.6: MRS on page 74, 3.7.7: MSR on page 75, and

3.7.2: CPS on page 70 for more information.

Priority Mask Register

The PRIMASK register prevents activation of all exceptions with configurable priority. See

the register summary in Table 3 on page 13 for its attributes. The bit assignments are:

CONTROL register

The CONTROL register controls the stack used, and the privilege level for software execu-

tion, when the processor is in Thread mode. See the register summary in Table 3 on

page 13 for its attributes. The bit assignments are:

Table 8. PRIMASK register bit assignments

Bits

Name

Function

[31:1]

Reserved.

[0]

Prioritizable interrupt mask:

0 = No effect.

1 = Prevents the activation of all exceptions with configurable priority.

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