PM0223 datasheet(85/110 Pages) STMICROELECTRONICS

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PM0223

STM32L0 Core Peripherals

108

Note:

Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding

interrupt.

4.2.6

Interrupt Priority Registers

The NVIC_IPR0-NVIC_IPR7 registers provide an 8-bit priority field for each interrupt. These

registers are only word-accessible. See the register summary in Table 26 on page 82 for

their attributes. Each register holds four priority fields as shown:

See 4.2.1: Accessing the STM32L0 Cortex-M0+ NVIC registers using CMSIS on page 82

for more information about the access to the interrupt priority array, which provides the

software view of the interrupt priorities.

Bits 31:0 CLRPEND: Interrupt clear-pending bits

Write:

0: No effect

1: Removes pending state and interrupt.

Read:

0: Interrupt is not pending

1: Interrupt is pending

Table 28. NVIC_IPRx bit assignments

Bits

Name

Function

[31:24]

Priority, byte offset 3

Each priority field holds a priority value, 0-192. The

lower the value, the greater the priority of the

corresponding interrupt. The processor implements

only bits[7:6] of each field, bits [5:0] read as zero

and ignore writes. This means writing 255 to a

priority register saves value 192 to the register.

[23:16]

Priority, byte offset 2

[15:8]

Priority, byte offset 1

[7:0]

Priority, byte offset 0

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